RTL Design Engineer

We’re looking for an experienced ASIC RTL Engineer to own end-to-end design for complex SoC/subsystem blocks—from micro-architecture to tapeout and silicon bring-up.Key

Requirements:
✔ Strong SystemVerilog/Verilog & micro-architecture skills
✔ Experience owning multiple ASIC tapeouts
✔ Hands-on low-power design (UPF), clock/reset, AXI/AMBA protocols
✔ Worked closely with PD, DFT, DV, and silicon teams
✔ Proven silicon bring-up experienceNice to Have: Coherency, memory controllers, DDR/PCIe, security blocks, SVA, scripting.

⏳ Notice Period: 0–60 Days (Early joiners preferred)

Job Types: Full-time, Permanent

Benefits:

• Health insurance
• Paid sick time
• Provident Fund

Work Location: In person