Silicon Package Designer

Job Title: Silicon Package Designer
Location: Santa Clara, CA

This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies.

Tools & Knowledge:
Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).

Technical Expertise:
Multi-layer package design experience.
Understanding of substrate manufacturing Design Rules and Assembly Rules.
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
Flip-chip package design concepts.

Tasks:
Perform point-to-point connections.
Run DRC (Design Rule Checks), identify root causes, and fix issues.
Execute design based on provided schematics, including component placement and constraint setup.

Job Type: Full-time

Pay: $145,000.00 per year

Benefits:

• Dental insurance
• Health insurance
• Paid time off

Work Location: In person