Qureos Mentor

聯發科技

Job Description: Mediatek Egypt is seeking a skilled and motivated Digital Design to join our high-performance team focusing on SerDes and high-speed interface IP development. The successful candidate will be responsible for the architecture, RTL design, and integration of PHY IP blocks, collaborating with cross-functional teams to ensure high-quality and robust IP solutions for cutting-edge SoCs. Key Responsibilities: Technical Leadership: Provide strategic direction and technical guidance to the engineering team, fostering innovation and ensuring the implementation of best practices in PHY IP development. PHY IP Architecture Planning: Contribute to the architectural design of PHY IPs for high-speed interfaces such as Ethernet SerDes, USB, PCIe, HDMI, DisplayPort, MPHY, and CPHY. RTL Design &amp; Coding: Develop and implement RTL code for PHY IPs with a focus on performance, power efficiency, and silicon area optimization. Front-end and Back-end Integration: Handle the integration of PHY IPs in both front-end and back-end design flows, ensuring seamless connectivity and function within the SoC. Cross-functional Collaboration: Work closely with MAC design and Design Verification (DV) teams for system-level IP verification. Collaborate with analog design teams for PHY/SerDes co-simulation and mixed-signal integration.
 Required Qualifications: Bachelor's degree in communication and Electronics Engineering, Computer Engineering Provide technical leadership and guidance to the engineering team, ensuring best practices and innovative solutions are implemented. Proficiency in RTL design for digital circuits Familiarity with front-end and back-end integration flows, as well as EDA tools. Practical experience in PHY IP development for high-speed interfaces A solid understanding of high-speed interface standards, including Ethernet SerDes, PCIe, USB, HDMI, DP, MPHY, and CPHY. Knowledge of DSP-based IP design techniques, such as CDR, CTLE, FEC, FIR, and IIR. Preferred Skills: Leadership skills and the ability to inspire and guide team members. Strong problem-solving and debugging abilities. Effective teamwork skills. Excellent communication and documentation capabilities. #LI-AK1

Staff Digital Design Engineer

The Analog Design and Circuit Technology team at MediaTek Egypt is searching for qualified candidates to join our fast-growing team. As a member of this dynamic team, you will get to work on state-of-the-art next generation wireline and optical transceivers for data centers serving cloud infrastructure as well as the growing field of AI and high-performance computing. We are looking for ambitious layout engineers, who are willing to learn, grow and contribute to diverse portfolio of products. Job Description: &bull;Own full-custom layout for analog and mixed-signal IPs (e.g., ADCs, PLLs, LDOs, bandgaps, high-speed interfaces) &bull;Work closely with circuit designers to optimize layout for performance and area. &bull;Perform detailed floor planning and transistor-level layout &bull;Ensure designs are DRC/LVS/ERC clean and meet all physical verification requirements &bull;Support post-layout simulations and sign-off procedures &bull;Handle LDE, EM/IR, and parasitic effects in advanced process nodes
 &bull;BSc in EE or higher &bull;Proficient in Cadence Virtuoso, Calibre, and physical verification tools &bull;Deep understanding of analog layout best practices and layout-dependent effects &bull;Team-oriented with strong communication and problem-solving skills &bull;Strong communication skills, team-player and good working attitude. #LI-AK1

Senior/Staff Layout engineer

Job Description: Mediatek Egypt is seeking a skilled and motivated Digital Design to join our high-performance team focusing on SerDes and high-speed interface IP development. The successful candidate will be responsible for the architecture, RTL design, and integration of PHY IP blocks, collaborating with cross-functional teams to ensure high-quality and robust IP solutions for cutting-edge SoCs. Key Responsibilities: PHY IP Architecture Planning: Contribute to the architectural design of PHY IPs for high-speed interfaces such as Ethernet SerDes, USB, PCIe, HDMI, DisplayPort, MPHY, and CPHY. RTL Design &amp; Coding: Develop and implement RTL code for PHY IPs with a focus on performance, power efficiency, and silicon area optimization. Front-end and Back-end Integration: Handle the integration of PHY IPs in both front-end and back-end design flows, ensuring seamless connectivity and function within the SoC. Cross-functional Collaboration: Work closely with MAC design and Design Verification (DV) teams for system-level IP verification. Collaborate with analog design teams for PHY/SerDes co-simulation and mixed-signal integration.
 Required Qualifications: Bachelor's degree in communication and Electronics Engineering, Computer Engineering Proficiency in RTL design for digital circuits Familiarity with front-end and back-end integration flows, as well as EDA tools. Practical experience in PHY IP development for high-speed interfaces A solid understanding of high-speed interface standards, including Ethernet SerDes, PCIe, USB, HDMI, DP, MPHY, and CPHY. Knowledge of DSP-based IP design techniques, such as CDR, CTLE, FEC, FIR, and IIR is preferred. Preferred Skills: Strong problem-solving and debugging abilities. Effective teamwork skills. Excellent communication and documentation capabilities. Required Qualifications: Bachelor's degree in communication and Electronics Engineering, Computer Engineering Proficiency in RTL design for digital circuits Familiarity with front-end and back-end integration flows, as well as EDA tools. Practical experience in PHY IP development for high-speed interfaces A solid understanding of high-speed interface standards, including Ethernet SerDes, PCIe, USB, HDMI, DP, MPHY, and CPHY. Knowledge of DSP-based IP design techniques, such as CDR, CTLE, FEC, FIR, and IIR is preferred. Preferred Skills: Strong problem-solving and debugging abilities. Effective teamwork skills. Excellent communication and documentation capabilities. #LI-AK1

Senior Digital Design Engineer

Mediatek Egypt is seeking a skilled and motivated Digital Design to join our high-performance team focusing on SerDes and high-speed interface IP development. The successful candidate will be responsible for the architecture, RTL design, and integration of PHY IP blocks, collaborating with cross-functional teams to ensure high-quality and robust IP solutions for cutting-edge SoCs. Key Responsibilities: RTL Design &amp; Coding: Develop and implement RTL code for PHY IPs with a focus on performance, power efficiency, and silicon area optimization. Front-end and Back-end Integration: Handle the integration of PHY IPs in both front-end and back-end design flows, ensuring seamless connectivity and function within the SoC. Cross-functional Collaboration: Work closely with MAC design and Design Verification (DV) teams for system-level IP verification. Collaborate with analog design teams for PHY/SerDes co-simulation and mixed-signal integration.
 Required Qualifications: Bachelor's degree in communication and Electronics Engineering, Computer Engineering Experience in RTL design for digital circuits Familiarity with front-end and back-end integration flows, as well as EDA tools. Practical experience in PHY IP development for high-speed interfaces is preferred. Preferred Skills: Problem-solving and debugging abilities. Effective teamwork skills. Excellent communication and documentation capabilities. Required Qualifications: Bachelor's degree in communication and Electronics Engineering, Computer Engineering Proficiency in RTL design for digital circuits Familiarity with front-end and back-end integration flows, as well as EDA tools. Practical experience in PHY IP development for high-speed interfaces A solid understanding of high-speed interface standards, including Ethernet SerDes, PCIe, USB, HDMI, DP, MPHY, and CPHY. Knowledge of DSP-based IP design techniques, such as CDR, CTLE, FEC, FIR, and IIR is preferred. Preferred Skills: Strong problem-solving and debugging abilities. Effective teamwork skills. Excellent communication and documentation capabilities. #LI-AK1

Digital Design Engineer

The Analog Design and Circuit Technology team at MediaTek Egypt is searching for qualified candidates to join our fast-growing team. As a member of this dynamic team, you will get to work on state-of-the-art next generation wireline and optical transceivers for data centers serving cloud infrastructure as well as the growing field of AI and high-performance computing. We are looking for ambitious analog and mixed signal design engineers who are willing to learn, grow and contribute to diverse portfolio of products. Job Description: &bull;Architecture study and evaluation of advanced SerDes topologies such as 112Gbps PAM-4 and beyond &bull;SerDes design and verification of different high speed analog and mixed signal blocks including, but not limited to: drivers, front end circuits, samplers, comparators, ADCs, DACs, PLLs, clock distribution, etc. &bull;Evaluate, measure, and debug silicon until it reaches high volume production. &bull;Work with cross functional teams to optimize the designs.
 Requirement : &bull;BSc and above with a major in EE or Physics related field. &bull;Solid background in analog CMOS circuit design. &bull;Proficient with Cadence design environment and mixed-signal simulation. &bull;Able to assume responsibility for a variety of technical tasks and to work independently. &bull;(recommended) Digital communication system, digital signal processing, digital system design, RF system, MATLAB #LI-AK1

Analog mixed signal design engineer