Qureos Mentor

<div>
 <strong>
  WHAT YOU DO AT AMD CHANGES EVERYTHING
  <br/>
  <br/>
 </strong>
 At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
 <strong>
  Together, we advance your career.
  <br/>
  <br/>
 </strong>
 <strong>
  The Role
  <br/>
  <br/>
 </strong>
 This is a great opportunity to join a global supply chain organization to influence across functions &amp; regions (Finance, Business Units, Engineering), using your advanced product planning, analytical and problem-solving skills. We are seeking a Supply Chain Professional with NPI launch preparedness coordination, accuracy of supply plans for NPI/Sustaining products, cost/benefit analysis, and proactive inventory management.
 <br/>
 <br/>
 <strong>
  The Person
  <br/>
  <br/>
 </strong>
 The Product Planner will be recognized as the expert of his/her product portfolio, and will drive outstanding processes, reporting and communication on a global scale. You should be comfortable working in a fast-paced environment and be change tolerant. You should also have executive level presentation skills, and strong organizational, problem-solving &amp; analytical skills.
 <br/>
 <br/>
 <strong>
  Key Responsibilities
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Analyze supply-demand matching, based on MRP system, to determine root cause changes, shortages and surpluses, and identify and drive course corrections.
  </li>
  <li>
   Review all MRP inputs with functional owners to drive accountability and data accuracy (Yields, BOM, Capacity, etc.).
  </li>
  <li>
   Provide product intelligence and required actions in the generation of the inventory forecast.
  </li>
  <li>
   Articulate the difference between the demand plan (ship plan) and revenue plan (MOF). Drive discussion/ actions to close revenue commitment gaps by unit, and improve the overall health of the product(s).
  </li>
  <li>
   Recommend demand shaping opportunities to achieve business goals.
  </li>
  <li>
   Represent ISC and articulate supply and inventory plans at all meetings with key internal customers: PEO, Business Unit, and Production Control (PLPC). Examples: NPI Readiness/PM, Core Team, SCT, ISC Ops.
  </li>
  <li>
   Drive disposition of inactive / hold inventory and represent ISC in meetings with the Business Units, Finance teams and Inventory Management.
  </li>
  <li>
   Identify required demand mix for factory planner to execute to when managing the line and creating the Graded Die Forecast (GDF).
  </li>
  <li>
   Manage OPN Constraints to align release dates, based on IP date and or manufacturing requirements.
  </li>
  <li>
   Coordinate with data management (GPDM) for new BOM creation, based on new RIDV and post-processors.
  </li>
  <li>
   Meet with Central Planning to identify part connections / disconnections in the BOM.
   <br/>
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  Preferred Experience
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Proven 7+ years of experience with Product Planning
  </li>
  <li>
   Knowledge of semiconductor manufacturing environment
  </li>
  <li>
   Advanced supply chain analysis skills, as well as advanced Excel and Power Point skills
  </li>
  <li>
   Advanced knowledge of Manufacturing and Inventory Management.
  </li>
  <li>
   Know-how of supply chain theory and processes, operational execution &amp; operations needs are critical.
  </li>
  <li>
   Demonstrated ability to collaborate at all levels of the organization.
  </li>
  <li>
   Experience working in a semiconductor company or OSAT, with strong understanding of logistical system processes desired
  </li>
  <li>
   Advanced Planning system experience
   <br/>
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  Academic Credentials
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   BS or MS in Supply Chain, Industrial engineering / Operations or Business is preferred
   <br/>
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  Location:
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Austin, Texas
   <br/>
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  This role is not eligible for Visa sponsorship.
  <br/>
  <br/>
 </strong>
 <em>
  Benefits offered are described:
 </em>
 AMD benefits at a glance.
 <br/>
 <br/>
 <em>
  AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.
  <br/>
  <br/>
 </em>
 <em>
  AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available here.
  <br/>
  <br/>
 </em>
 <em>
  This posting is for an existing vacancy.
  <br/>
  <br/>
 </em>
</div>


Supply Chain Specialist

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>Role Summary</b></div><div>
AMD is seeking a highly motivated engineer to drive the next generation of <b>Unified Power-Frequency Modeling (UPFM)</b> used across our CPU, GPU, and APU product roadmap. The ideal candidate will be passionate about bridging <b>pre-silicon architecture modeling</b>, <b>post-silicon measurement</b>, and <b>system-level power optimization</b>, helping AMD deliver industry-leading performance-per-watt in modern compute platforms.</div><div>
This role provides a unique opportunity to operate across the full silicon lifecycle&mdash;developing analytical models, integrating silicon calibration data, and enabling productization of advanced adaptive power features such as AVFS, hierarchical binning, and chiplet-level optimization.</div><div>
You will be a core contributor to UPFM evolution, ensuring that predictive modeling, silicon telemetry, and field data are tightly coupled in a continuously-learning modeling pipeline.</div><p></p><div><b>
Key Responsibilities</b></div><ul><li>
Expand UPFM to incorporate emerging IPs, new technology nodes, aging models, and hierarchical SoC/power-management structures.</li><li>
Build parameterized analytical models capturing:<ul><li><b>
Dynamic and static power</b>,</li><li><b>
Voltage&ndash;frequency scaling</b>,</li><li><b>
Critical-path delay and FO2-based timing</b>,</li><li><b>
Workload-dependent switching behavior</b>,</li><li><b>
Process variation effects (leakage, Vmin, RC, mobility)</b>.</li></ul></li><li>
Integrate <b>silicon data</b> into model calibration loops; refine UPFM coefficients across product generations.</li><li>
Develop modeling infrastructure to support early-stage architecture planning and power budgeting. Also enable the evaluation of ROI of new power features and power-delivery innovations.</li><li>
Work closely with architecture, design, firmware, and production teams to ensure modeling accuracy and feature success.</li><li>
Support product engineers in chiplet binning, AVFS tuning, yield/power analysis, and field-return analysis.</li><li>
Collaborate with system teams to extend UPFM for chiplet-based systems and datacenter power constraints.</li><li>
Develop and maintain Python/Ruby-based modeling pipelines, data-processing infrastructure, and visualization dashboards.</li><li>
Automate ingestion of silicon data into UPFM to support continuous model evolution.</li><li>
Build scripts for sensitivity analysis, Monte Carlo modeling, regression, and parametric sweep automation.</li></ul><p></p><div><b>
Preferred Experience</b></div><div>
Candidates with expertise in one or more of the following are strongly encouraged to apply:</div><div><b>
Power &amp; Performance Modeling</b></div><ul><li>
Experience modeling power for digital/analog IPs (CPUs, GPUs, accelerators).</li><li>
Familiarity with switching power, leakage mechanisms, IR drop, and timing/power interactions.</li><li>
Knowledge of V/F behavior, clocking, AVFS, voltage guardbands, and power-management architectures.</li></ul><div><b>
Silicon Correlation &amp; Variation Modeling</b></div><ul><li>
Understanding of silicon variability (process variation, Vmin, FO2 timing spread, aging).</li><li>
Familiarity with statistical modeling, Monte Carlo analysis, or UPFM-like frameworks.</li><li>
Experience analyzing ring oscillator data, telemetry, or embedded monitors.</li></ul><div><b>
Design, Firmware &amp; Debug Knowledge</b></div><ul><li>
Working knowledge of digital logic design, RTL fundamentals, and physical design constraints.</li><li>
Understanding of clock gating, power gating, voltage domains, and on-die regulation.</li><li>
Exposure to design-for-debug, PSS, or validation toolchains.</li></ul><div><b>
Programming &amp; Data Analysis</b></div><ul><li>
Strong experience with Python (NumPy/Pandas/Scipy), Excel modeling, and scripting.</li><li>
Database experience (SQL, Parquet, analytics pipelines) is a plus.</li><li>
Ability to build reproducible modeling environments and automated analysis tools.</li></ul><p></p><div><b>
Education Requirements</b></div><ul><li>
M.S. or Ph.D. in <b>Electrical Engineering</b>, <b>Computer Engineering</b>, <b>Computer Science</b>, <b>Applied Physics</b>, or related field with 4+ years of relevant experience<br>
<b>OR</b></li><li>
B.S. with 6+ years of industry experience in power modeling, silicon analysis, or performance engineering.</li></ul><p></p><div><b>
Ideal Candidate Profile</b></div><div>
The ideal candidate is:</div><ul><li>
Strong in <b>mathematical modeling</b>, <b>silicon physics</b>, and <b>systems thinking</b>.</li><li>
Excited to work hands-on with both models and real silicon data.</li><li>
Able to operate across architecture, design, and product disciplines.</li><li>
Passionate about building frameworks that guide billion-dollar product decisions.</li>
Comfortable owning end-to-end solutions&mdash;from analysis modeling calibration<li> productization.</li></ul><div>
</div>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div><div></div><div><i><br>
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available </i><i>here.</i></div><div></div><div><i><br>
This posting is for an existing vacancy.</i></div></div>

Senior Power & Performance Modeling Engineer (UPFM)

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
UPFM Support: Senior SILICON DESIGN ENGINEER</b></div><div></div><div><br>
The goal of AMD&rsquo;s Unified Power Flow Methodology (UPFM) is to establish and scale best practices for power intent definition and power-aware design across RTL, implementation, verification, and sign-off. UPFM drives consistent use of industry-standard formats (e.g., UPF) and enables automation so design teams can reliably achieve aggressive PPA (performance, power, area) targets while meeting low-power architecture requirements (isolation, level shifting, retention, power gating, DVFS). The UPFM team partners closely with front‑end, physical design, verification, and sign‑off teams to integrate power intent seamlessly into next‑generation GPUs, CPUs, and APUs using leading EDA tools and flows (e.g., Synopsys, Cadence, Siemens).</div><div></div><div><b><br>
JOB PURPOSE:</b></div><div>
Build, deploy, and support a world‑class, power‑aware design flow (UPF‑based) in a fast‑paced production environment&mdash;enabling robust low‑power architectures, first‑time-right integration, and predictable sign‑off across multiple programs and nodes.</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>Develop and maintain UPF/low‑power methodology across RTL, synthesis, P&amp;R, STA, and verification.</li><li>Own flow features for power intent generation, validation, and ingestion (UPF authoring, linting, merges, hierarchy management, ECOs).</li><li>Evaluate, qualify, and tune power‑aware capabilities in EDA tools (e.g., synthesis, implementation, CDC/RDC, PA‑simulation, formal LP checks, EM/IR/thermal).</li><li>Support place-and-route flows for power features: isolation/retention insertion, level shifters, power switch strategies, power domain floorplanning, power grid integration.</li><li>Build automation for consistency and scalability (templates, generators, checkers, dashboards; CI integration).</li><li>Deploy flows to design teams, drive training, documentation, and best practices; troubleshoot complex issues across tool/flow/design boundaries.</li><li>Partner with architects and design leads to capture power requirements (domains, states, transitions) and translate them into actionable UPF/constraints.</li><li>Ensure sign‑off closure for low‑power: UPF vs RTL/Netlist consistency, PA‑CDC/RDC, PA‑STA, LVS/DRC implications, EM/IR with multi‑domain scenarios.</li><li>Lead cross‑team debug for power‑aware failures (X‑propagation, state retention, clamp behavior, wake/sleep sequences, corner interactions).</li><li>Mentor junior engineers to scale UPFM capabilities and improve overall team productivity.</li></ul><div></div><div><b><br>
SKILLS AND EXPERIENCE REQUIREMENTS:</b></div><ul><li>Bachelor&rsquo;s in Electrical/Computer Engineering and 5+ years low‑power/UPF/CAD experience, or Master&rsquo;s with 3+ years experience.</li><li>Strong understanding of digital design and low‑power architecture: power domains/states, isolation/retention, level shifters, power gating, DVFS, multi‑rail implications.</li><li>Expert‑level UPF (IEEE 1801) authoring and integration across RTL synthesis P&amp;R verification sign‑off.</li><li>Hands‑on with power‑aware EDA tools (representative examples):</li><li><b>Front‑end/Verification:</b> Synopsys VCS + VC LP/Verdi; Cadence Xcelium/Conformal LP; Siemens Questa PA.</li><li><b>Synthesis/Implementation:</b> Synopsys Design Compiler/Fusion/ICC2; Cadence Genus/Innovus.</li><li><b>Timing/Sign‑off:</b> Synopsys PrimeTime/PrimePower; Cadence Tempus; static LP checkers and PA‑CDC/RDC tools.</li><li><b>Power Integrity:</b> Ansys RedHawk‑SC; Cadence Voltus (EM/IR with multi‑domain analysis).</li><li>Excellent UNIX and scripting skills (Tcl mandatory; Python and/or Perl strongly preferred); experience building flow automation and CI pipelines.</li><li>Proven experience with constraint management for multi‑domain designs (clock/power intent coherence, PA‑STA).</li><li>Familiarity with CDC/RDC methodologies under power‑aware conditions (domain on/off interactions, clamp strategies).</li><li>Experience with version control (Perforce, Git) and collaborative tooling; strong documentation and training skills.</li><li>Outstanding communication, analytical debugging, and cross‑functional collaboration; highly motivated, self‑starter.</li></ul><div></div><div><b><br>
NICE‑TO‑HAVE:</b></div><ul><li>Experience with multi‑chip/3D IC power intent integration (chiplet, package‑aware flows).</li><li>Knowledge of power‑aware DFT/scan strategies (retention across test, power domains in ATPG).</li><li>Exposure to power telemetry/monitoring IP and firmware interactions (state orchestration).</li><li>Familiarity with power management controllers and sequencing validation (UPF states/transitions).</li></ul><div><div><b>
Role Summary</b></div><div>
AMD is seeking a highly motivated engineer to drive the next generation of <b>Unified Power-Frequency Modeling (UPFM)</b> used across our CPU, GPU, and APU product roadmap. The ideal candidate will be passionate about bridging <b>pre-silicon architecture modeling</b>, <b>post-silicon measurement</b>, and <b>system-level power optimization</b>, helping AMD deliver industry-leading performance-per-watt in modern compute platforms.</div><div>
This role provides a unique opportunity to operate across the full silicon lifecycle&mdash;developing analytical models, integrating silicon calibration data, and enabling productization of advanced adaptive power features such as AVFS, hierarchical binning, and chiplet-level optimization.</div><div>
You will be a core contributor to UPFM evolution, ensuring that predictive modeling, silicon telemetry, and field data are tightly coupled in a continuously-learning modeling pipeline.</div><p></p><div><b>
Key Responsibilities</b></div><ul><li>
Expand UPFM to incorporate emerging IPs, new technology nodes, aging models, and hierarchical SoC/power-management structures.</li><li>
Build parameterized analytical models capturing:<ul><li><b>
Dynamic and static power</b>,</li><li><b>
Voltage&ndash;frequency scaling</b>,</li><li><b>
Critical-path delay and FO2-based timing</b>,</li><li><b>
Workload-dependent switching behavior</b>,</li><li><b>
Process variation effects (leakage, Vmin, RC, mobility)</b>.</li></ul></li><li>
Integrate <b>silicon data</b> into model calibration loops; refine UPFM coefficients across product generations.</li><li>
Develop modeling infrastructure to support early-stage architecture planning and power budgeting. Also enable the evaluation of ROI of new power features and power-delivery innovations.</li><li>
Work closely with architecture, design, firmware, and production teams to ensure modeling accuracy and feature success.</li><li>
Support product engineers in chiplet binning, AVFS tuning, yield/power analysis, and field-return analysis.</li><li>
Collaborate with system teams to extend UPFM for chiplet-based systems and datacenter power constraints.</li><li>
Develop and maintain Python/Ruby-based modeling pipelines, data-processing infrastructure, and visualization dashboards.</li><li>
Automate ingestion of silicon data into UPFM to support continuous model evolution.</li><li>
Build scripts for sensitivity analysis, Monte Carlo modeling, regression, and parametric sweep automation.</li></ul><p></p><div><b>
Preferred Experience</b></div><div>
Candidates with expertise in one or more of the following are strongly encouraged to apply:</div><div><b>
Power &amp; Performance Modeling</b></div><ul><li>
Experience modeling power for digital/analog IPs (CPUs, GPUs, accelerators).</li><li>
Familiarity with switching power, leakage mechanisms, IR drop, and timing/power interactions.</li><li>
Knowledge of V/F behavior, clocking, AVFS, voltage guardbands, and power-management architectures.</li></ul><div><b>
Silicon Correlation &amp; Variation Modeling</b></div><ul><li>
Understanding of silicon variability (process variation, Vmin, FO2 timing spread, aging).</li><li>
Familiarity with statistical modeling, Monte Carlo analysis, or UPFM-like frameworks.</li><li>
Experience analyzing ring oscillator data, telemetry, or embedded monitors.</li></ul><div><b>
Design, Firmware &amp; Debug Knowledge</b></div><ul><li>
Working knowledge of digital logic design, RTL fundamentals, and physical design constraints.</li><li>
Understanding of clock gating, power gating, voltage domains, and on-die regulation.</li><li>
Exposure to design-for-debug, PSS, or validation toolchains.</li></ul><div><b>
Programming &amp; Data Analysis</b></div><ul><li>
Strong experience with Python (NumPy/Pandas/Scipy), Excel modeling, and scripting.</li><li>
Database experience (SQL, Parquet, analytics pipelines) is a plus.</li><li>
Ability to build reproducible modeling environments and automated analysis tools.</li></ul><p></p><div><b>
Education Requirements</b></div><ul><li>
M.S. or Ph.D. in <b>Electrical Engineering</b>, <b>Computer Engineering</b>, <b>Computer Science</b>, <b>Applied Physics</b>, or related field with 2+ years of relevant experience<br>
<b>OR</b></li><li>
B.S. with 4+ years of industry experience in power modeling, silicon analysis, or performance engineering.</li></ul><p></p><div><b>
Ideal Candidate Profile</b></div><div>
The ideal candidate is:</div><ul><li>
Strong in <b>mathematical modeling</b>, <b>silicon physics</b>, and <b>systems thinking</b>.</li><li>
Excited to work hands-on with both models and real silicon data.</li><li>
Able to operate across architecture, design, and product disciplines.</li><li>
Passionate about building frameworks that guide billion-dollar product decisions.</li>
Comfortable owning end-to-end solutions&mdash;from analysis modeling calibration<li> productization.</li></ul><div>
</div></div>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div><div></div><div><i><br>
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available </i><i>here.</i></div><div></div><div><i><br>
This posting is for an existing vacancy.</i></div></div>

Power, Performance & Silicon Modeling Engineer

<div>
 <strong>
  WHAT YOU DO AT AMD CHANGES EVERYTHING
  <br/>
  <br/>
 </strong>
 At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
 <strong>
  Together, we advance your career.
  <br/>
  <br/>
 </strong>
 <strong>
  MTS SOFTWARE DEVELOPMENT ENGINEER
  <br/>
  <br/>
 </strong>
 <strong>
  The Role
  <br/>
  <br/>
 </strong>
 AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks
 <strong>
  .
 </strong>
 You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology.
 <br/>
 <br/>
 <strong>
  The Person
  <br/>
  <br/>
 </strong>
 The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD.
 <br/>
 <br/>
 <strong>
  Key Responsibilities
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Design, implement and debug QEMU based virtual platforms
  </li>
  <li>
   Debugging/fix existing issues and research alternative, more efficient ways to accomplish the same work
  </li>
  <li>
   Apply a data minded approach to target optimization efforts
  </li>
  <li>
   Work with AMD&rsquo;s architecture specialists to improve future products
  </li>
  <li>
   Design and develop new groundbreaking AMD technologies
  </li>
  <li>
   Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture
   <br/>
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  Preferred Experience
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Experience with writing models for QEMU or other virtual platforms.
  </li>
  <li>
   Expert knowledge and hands-on experience in C, C++, git.
  </li>
  <li>
   Experience with Linux Device trees and Linux or baremetal driver development
  </li>
  <li>
   Experience with Embedded Linux and Embedded System development
  </li>
  <li>
   Experience with collaboration with Open Source projects
  </li>
  <li>
   Knowledge in ARM system architecture is considered a plus
  </li>
  <li>
   Effective communication and problem-solving skills
   <br/>
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  Academic Credentials
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Bachelor&rsquo;s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent
   <br/>
   <br/>
   <br/>
  </li>
 </ul>
 <em>
  Benefits offered are described:
 </em>
 AMD benefits at a glance.
 <br/>
 <br/>
 <em>
  AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.
  <br/>
  <br/>
 </em>
 <em>
  AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available here.
  <br/>
  <br/>
 </em>
 <em>
  This posting is for an existing vacancy.
  <br/>
  <br/>
 </em>
</div>


MTS Software Development Eng.

Join AMD and explore 4   exciting career opportunities. They're hiring for various roles with options for remote or on-site work. Apply today and become part of their innovative team.

AMD

ABOUT_COMPANY

Supply Chain Specialist

Senior Power & Performance Modeling Engineer (UPFM)

Power, Performance & Silicon Modeling Engineer

MTS Software Development Eng.