Qureos Mentor

<p></p><div><p><b>Job ID</b> 2025-16353</p>
<p><b>Date posted</b> Dec. 08, 2025</p>
<p><b>Location</b> Bengaluru, India
</p><p><b>Category</b> Hardware Engineering, Design Engineering</p></div><p></p>
<br><p></p><div><p>Responsibilities:</p><ul><li>
Work with design team to develop design intent, timing constraints required to enable implementation.</li><li>
Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC</li><li>
Analyze design timing, area and power to help improve the quality of ARM IP</li><li>
Develop and deploy new methodologies to improve implementation efficiency and results</li><li>
Support and develop detailed implementation analysis and data-mining methodologies.</li><li>
Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.</li><li>
Converting R&amp;D concepts into real implementation solutions.</li><li>
Enable our partners to achieve the best possible quality of results.</li></ul><p>
Required Skills and Experience :</p><ul><li>
Bachelors or Master&rsquo;s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.</li><li>
7+ years of proven experience in ASIC Implementation, Synthesis, Timing constraints, UPF, Physical design, STA and Timing closure, Structured clock tree, PDN analysis</li><li>
The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills.</li><li>
Experience in crafting and embracing new silicon implementation techniques and methodologies and promote their use with international teams</li><li>
Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Confirmed programming and scripting skills eg. Tcl, Perl, R, Make, sh.</li></ul><p></p><div><i>
Our </i><b>10x mindset </b><i>guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work:</i><div>https://careers.arm.com/en/10x-mindset</div></div><p></p><div><div><div><div><div><div><div><div><div><div><p>
#LI-RS4</p></div></div></div></div></div></div></div></div></div></div><p>
Accommodations at Arm</p><p>
At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.</p><p>
Hybrid Working at Arm</p><p>
Arm&rsquo;s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team&rsquo;s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.</p><p>
Equal Opportunities at Arm</p><p>
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don&rsquo;t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.</p></div>

Senior Physical Design Engineer - PNR

<p></p><div><p><b>Job ID</b> 2025-13804</p>
<p><b>Date posted</b> Dec. 01, 2025</p>
<p><b>Location</b> Austin, Texas; Raleigh, North Carolina
</p><p><b>Category</b> Hardware Engineering, Design Engineering</p></div><p></p>
<br><div><p>About Arm</p><p>
Arm is the industry&rsquo;s leading supplier of microprocessor technology, offering the widest range of microprocessor cores to address the performance, power, and cost requirements for almost all application markets. With a vibrant ecosystem of over 1,000 partners and more than 150 billion processors shipped, our technology is at the heart of a computing and connectivity revolution that continues to transform the way people live and businesses operate.</p><p>
Job Overview</p><p>
The Issue/Scheduler unit is central to an out-of-order CPU&rsquo;s performance and PPA. As the Principal (G6) for this unit you will take ownership of the RTL implementation that tracks renamed micro-ops, determines operand readiness, and issues ready uops to execution pipelines. You will lead the design choices for distributed issue-queues, wakeup/select logic, register file design, forwarding/result-cache interfaces and dispatch steering, and will be accountable for the unit&rsquo;s PPA, RTL quality and cross-functional integration. This is a high-visibility role with strong technical leadership and delivery expectations.</p><p>
Responsibilities</p><ul><li><b>
Own the Issue/Scheduler unit delivery</b> &mdash; translate microarchitecture specifications into an executable RTL plan, drive implementation to meet performance, power and area (PPA) targets, and enforce RTL quality across the unit.</li><li><b>
Drive PPA and power/energy optimization</b> &mdash; lead efforts to lower power, quantify energy vs performance impacts and deliver measurable improvements without regressing IPC.</li><li><b>
Champion verification &amp; prototyping</b> &mdash; Collaborate with verification team on unit verification strategies, own prototyping and RTL closure activities, own documentation (including I/O specs) and ensure robust cross-discipline validation with Verification, Performance and Physical design teams.</li><li><b>
Lead and mentor</b> &mdash; provide technical leadership and mentorship for engineers, lead technical reviews, and present design decisions and tradeoffs to senior stakeholders.</li></ul><p>
Required skills and experience</p><ul><li><b>
Extensive microarchitecture experience (typical 10+ years)</b> in out-of-order CPUs, with direct ownership or design leadership for issue/wakeup/select/register file/scheduling logic and instruction dispatch subsystems.</li><li><b>
Proven RTL ownership and delivery</b> &mdash; track record translating uarch specs into RTL, collaborating with physical design team to meet PPA and schedule, and enforcing RTL quality standards.</li><li><b>
Deep expertise in distributed issue-queue architectures</b> (multi-queue configurations, write/read port tradeoffs, staging/shift-once behavior and age/oldest selection).</li><li><b>
Demonstrated PPA/energy optimization experience</b> &mdash; ability to design and quantify architecture/RTL changes that trade performance, power and area effectively.</li><li><b>
Verification and prototyping leadership</b> &mdash; experience defining verification strategies, leading closure efforts and working closely with verification teams to validate complex CPU IP.</li><li><b>
Excellent communication, stakeholder management and mentorship skills</b> &mdash; able to lead technical reviews and represent the unit across the CPU program.</li><li><b>
Proficiency in RTL and toolchain</b> (Verilog/SystemVerilog/VHDL or equivalent), synthesis constraints, timing closure practices and modern verification methodologies.</li></ul><p>
&ldquo;Nice to have&rdquo; skills and experience</p><ul><li>
Track record of <b>silicon/IP delivery</b> (tapeout or equivalent) for CPU microarchitecture blocks.</li><li>
Experience with performance-modelling and microarchitecture simulation frameworks to predict IPC, wakeup/select latency and dispatch behavior.</li><li>
Advanced degree (M.S./Ph.D.) in Computer/ Electrical Engineering or Computer Science, with specialization in computer architecture or microarchitecture research.</li><li>
Prior experience <b>leading a design unit</b> or multiple teams and defining unit RTL quality standards.</li></ul><p>
In Return</p><ul><li><b>
Influence next-generation CPU microarchitecture</b> &mdash; you&rsquo;ll shape core scheduling and Issue logic that directly determines performance for Arm CPUs.</li><li><b>
High-visibility, leadership role</b> &mdash; a chance to lead a critical unit, mentor engineers, set RTL quality standards and make design decisions with program-level impact.</li><li><b>
Work at the frontier of PPA and energy optimization</b> &mdash; apply and evaluate advanced techniques to reduce IQ energy while maintaining or improving IPC.</li><li><b>
Cross-functional collaboration and delivery</b> &mdash; partner with front-end, rename, verification, performance modelling and physical design teams to take concepts from spec through RTL, validation and delivery.</li></ul><p>
Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset</p><p></p><p>
#LI-RJ1</p><div><p>
Salary Range:</p><p>
$241,100-$326,100 per year</p><p>
We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.</p></div><p>
Accommodations at Arm</p><p>
At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.</p><p>
Hybrid Working at Arm</p><p>
Arm&rsquo;s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team&rsquo;s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.</p><p>
Equal Opportunities at Arm</p><p>
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don&rsquo;t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.</p></div>

Principal Issue/Scheduler, Lead RTL Designer

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Senior Physical Design Engineer - PNR

Principal Issue/Scheduler, Lead RTL Designer