Urwah Admin

Cadence Design Systems

<div><div>At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</div><div>
The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.</div><ul><li>
Candidate&rsquo;s background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development</li><li>
Working knowledge of a set of common SerDes standards and their electrical requirements is a plus</li><li>
Must have a thorough understanding of jitter and signal equalization techniques</li><li>
Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators</li><li>
Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment</li><li>
Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification</li><li>
Cadence tool experience, lab test experience, and design experience at &gt;10Gbps and in &lt;28nm technologies are a plus</li><li>
MS or PhD in EE</li></ul><div><i>
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.</i></div><div>
We&rsquo;re doing work that matters. Help us solve what others can&rsquo;t.</div></div>

Sr. Principal Analog IC Designer

<div><div>At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</div><div>
Sr. Account Executive located in the Bay Area, responsible for account management and quota achievement is designated territory.</div><div>
We&rsquo;re doing work that matters. Help us solve what others can&rsquo;t.</div></div>

Sr Account Executive II

<div><div>At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</div><div>
As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence&rsquo;s market-leading technologies in Synthesis, P&amp;R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&amp;D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies.</div><div>
At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&amp;D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills.</div><div>
Key Responsibilities</div><ul><li>
 Be part of team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff</li><li>
Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules</li><li>
Collaborate with team to conduct technical presentations and product demonstrations</li><li>
Drive technical evaluations/benchmarks to success</li><li>
Work closely with R&amp;D to enhance the tools and methodologies to meet and exceed customer&rsquo;s requirements</li><li>
Drive adoption and proliferation of Cadence tools and technologies</li><li>
Provide guidance to the team to amend &amp; augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows</li><li>
Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements</li></ul><div>
Job Requirements</div><div>
Minimum</div><ul><li>
10+ years of industry Physical Design experience</li><li>
BS degree Computer Science/Engineering, Electrical, Engineering, or related field</li><li>
Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required</li><li>
Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure</li><li>
Experience with advanced nodes 10nm and below</li><li>
Experience in scripting languages such as Tcl/Perl/Python is a must</li><li>
Strong customer-facing communication and problem-solving skills</li><li>
Strong personal drive for continuous learning and expanding professional skill sets</li><li>
Strong verbal, written, and customer communication skills</li></ul><div>
Preferred</div><ul><li>
MS degree Computer Science/Engineering, Electrical, Engineering, or related field</li><li>
Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking</li><li>
Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired</li><li>
Experience with advanced nodes 5nm and below</li></ul><div></div><div><i>
The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.</i></div><div>
We&rsquo;re doing work that matters. Help us solve what others can&rsquo;t.</div></div>

Principal Application Engineer

<div><div>At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</div><div>
We offer amazing opportunities to grow, no matter where you are in your career.</div><div>
The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post&ndash;sales activities at advanced nodes for Cadence Digital IC products.</div><div></div><div>
Key Responsibilities</div><ul><li>
Provide technical support to Cadence customers in the areas of Digital Design Implementation &amp; Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff</li><li>
Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules</li><li>
Conduct technical presentations and product demonstrations</li><li>
Drive technical evaluations/benchmarks to success</li><li>
Work closely with R&amp;D to enhance the tools and methodologies to meet and exceed customer&rsquo;s requirements</li><li>
Drive adoption and proliferation of Cadence tools and technologies</li><li>
Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows</li><li>
Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements</li><li>
Provide technical support, when developing business case for process improvement projects.</li><li>
Provide mentorship to junior engineers</li></ul><div></div><div><br>
Job Requirements</div><ul><li>
Requires a BS or MS in EE with 3-7 years industry related experience in design and EDA (Digital Implementation/Signoff)</li><li>
Understands ASIC Design implementation process and steps</li><li>
Strong hands-on experience with Place &amp; Route (Innovus, ICC2, Fusion Compiler)</li><li>
Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler)</li><li>
Experience with EDA tools in the IC digital implementation &amp; signoff flows (STA tools)</li><li>
Strong STA and SDC debugging abilities are required.</li><li>
Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus.</li><li>
Automation skills using Perl, Tcl and shell scripting essential</li><li>
Strong analytical &amp; analysis skills covering digital implementation is critical.</li><li>
Proven track record and experience working in a fast paced environment</li><li>
Excellent customer interaction &amp; presentation skills</li></ul><div>
Be proud and passionate about the work you do. Together, our One Cadence - One Team culture drives our success.</div><div></div><div>
#LI-MA1</div><div><i>
The annual salary range for California is $102,900 to $191,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.</i></div><div>
We&rsquo;re doing work that matters. Help us solve what others can&rsquo;t.</div></div>

Lead Application- Digital Implementation

<div><div>At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</div><div>
As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence&rsquo;s market-leading technologies in Synthesis, P&amp;R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&amp;D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies.</div><div>
At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&amp;D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills.</div><div>
Key Responsibilities</div><ul><li>
Be part of team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff</li><li>
Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules</li><li>
Collaborate with team to conduct technical presentations and product demonstrations</li><li>
Drive technical evaluations/benchmarks to success</li><li>
Work closely with R&amp;D to enhance the tools and methodologies to meet and exceed customer&rsquo;s requirements</li><li>
Drive adoption and proliferation of Cadence tools and technologies</li><li>
Provide guidance to the team to amend &amp; augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows</li><li>
Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements</li></ul><div>
Job Requirements</div><div>
Minimum</div><ul><li>
5 years of industry Physical Design experience</li><li>
BS degree Computer Science/Engineering, Electrical, Engineering, or related field</li><li>
Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required</li><li>
Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure</li><li>
Experience with advanced nodes 10nm and below</li><li>
Experience in scripting languages such as Tcl/Perl/Python is a must</li><li>
Strong customer-facing communication and problem-solving skills</li><li>
Strong personal drive for continuous learning and expanding professional skill sets</li><li>
Strong verbal, written, and customer communication skills</li></ul><div>
Preferred</div><ul><li>
MS degree Computer Science/Engineering, Electrical, Engineering, or related field</li><li>
Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking</li><li>
Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired</li><li>
Experience with advanced nodes 5nm and below</li></ul><div></div><div><i>
The annual salary range for California is $102,900 to $191,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.</i></div><div>
We&rsquo;re doing work that matters. Help us solve what others can&rsquo;t.</div></div>

Lead Application Engineer