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Cadence Design Systems

<div><h2 class="jobSectionHeader">At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</h2>
This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality. The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control. The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies.
This includes but is not limited to:<ul><li>
Digital architecture that has an understanding of the trade-offs for power, performance, and area</li><li>
Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process</li><li>
Understanding of synthesis, constraint generation, power management and DFT</li><li>
Understanding of low-power designs and features (power islands, state retention, isolation)</li><li>
Work with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation</li><li>
Familiarity with uC Based subsystems and their architecture</li><li>
Familiarity with AI assisted design practices</li></ul>
Qualifications<ul><li>
18-20 years of experience in working with Digital Design and Architecture.</li><li>
Must have good written and verbal cross-functional communication skills.</li><li>
Proven experience in most of the following:<ul><li>
Design Architecture</li><li>
Design implementation</li><li>
Embedded uC Designs</li><li>
Synthesis and SDC Creation</li><li>
Scripting of design automation</li><li>
Debugging verification test cases / SVA&rsquo;s to cover the design</li></ul></li><li>
Knowledge of existing Serial standards such as PCIE, USB, Ethernet, etc.</li><li>
Must be comfortable interacting across the SSG development team including the ability to work with Mixed-signal, Verification and Analog teams</li><li>
Should be open to work with AI assisted design practices. Knowledge of AI assisted design flow is plus.</li><li>
Knowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus</li><li>
Working knowledge of revision control tools such as Perforce, Git, SVN is a plus</li><li>
Educational qualifications - minimum Bachelor&rsquo;s degree, Master&rsquo;s preferred</li></ul><h2 class="jobSectionHeader">
We&rsquo;re doing work that matters. Help us solve what others can&rsquo;t.</h2></div>

Design Architect

<div><h2 class="jobSectionHeader">At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</h2>
Job Description
Cadence Design Systems Inc. is looking for a motivated Software Engineer II: AI Compiler Engineer to work with us.
As a Software Engineer II: AI Compiler Engineer you will work with complex high performance SoC's, and is one of the best kept secrets within the semi IP world powering AR/VR, HiFi Audio and Speech, Vision, Imaging and hundreds of intelligent IoT applications.
Be a part of a team that develops an AI graph compiler that takes as input Neural Networks (NNs) created in frameworks such as PyTorch or TensorFlow and converts them into optimized code suitable for execution on special-purpose and embedded platforms.
Cadence is also a Fortune 100 Best Companies to Work For.
Job Description:<ul><li>
Developing a deep learning compiler stack that takes neural network descriptions (CNNs/RNNs) created in frameworks such as Caffe, PyTorch, TensorFlow, etc. and converts them into code suitable for execution on special-purpose and embedded platforms.</li><li>
Use modern compiler frameworks such as LLVM and MLIR.</li><li>
Developing optimized implementations of a variety of neural-network operations and integrating them into a runtime framework</li><li>
Developing new optimization techniques and algorithms to efficiently map CNNs onto a wide range of Xtensa processors and specialized hardware.</li><li>
Benchmarking end-to-end network performance on a variety of DSP and special-purpose accelerator platforms.</li><li>
Enhancing the framework to improve overall functionality and performance on the various hardware platforms.</li><li>
Devising multiprocessor/multicore partitioning and scheduling strategies.</li><li>
Developing complex programs to validate the functionality and performance of the CNN application programming kit.</li><li>
Working with hardware designers to identify opportunities for additional hardware acceleration of neural network functions.</li><li>
Working with industry-leading partners and customers to design and standardize neural network APIs..</li></ul>
Requirements:<ul><li>
Complete Bachelor in Computer Science or Computer Engineering or equivalent experience.</li><li>
A high level of C and C++ programming expertise with 3-5+ years of experience is required.</li><li>
Expertise in software development on Linux and Windows systems including test, debug and release is required.</li><li>
Knowledge of and experience with a state-of-the-art compiler stack such as LLVM and MLIR.</li><li>
Experience implementing compilation techniques such loop optimization, polyhedral models, and IR construction/transition/lowering techniques.</li></ul>
Nice to have:<ul><li>
Master or PhD.</li><li>
3+ years of experience working on a production compiler is highly desired.</li><li>
Python experience highly desired</li><li>
Prior work with CNNs and familiarity with deep learning frameworks (TensorFlow, Caffe/2, etc.) is a strong plus</li><li>
Experience programming and optimizing for embedded platforms such as DSPs with DMA engines highly desired</li><li>
Familiarity with the state-of-the-art deep learning compilation approaches (Glow, TVM, XLA, etc.) is a plus</li><li>
Familiarity with various deep learning networks and their applications (Classification/Segmentation/Object Detection/RNNs) is a plus</li><li>
Knowledge of neural net exchange formats (ONNX, NNEF) is a plus</li></ul>
Additional Job Details:<ul><li>
Employment term: 40 hours/week.</li><li>
Hybrid work.</li><li>
Competitive benefits.</li></ul>
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments.
For more information, access http://www.cadence.com<h2 class="jobSectionHeader">
We&rsquo;re doing work that matters. Help us solve what others can&rsquo;t.</h2></div>

Software Engineer II: AI Compiler Engineer

Join Cadence Design Systems and explore 2   exciting career opportunities. They're hiring for various roles with options for remote or on-site work. Apply today and become part of their innovative team.

Cadence Design Systems

About Company

Design Architect

Software Engineer II: AI Compiler Engineer