Qureos Mentor

L&T Semiconductor Technologies

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 Role : Sr Physical Design Lead/BE Integration
 
 
 This position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at Top level
 
 
 Key Responsibilities:
 
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 Expertise in hierarchical RTL2GDSII design implementation
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 Expertise in pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps
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 Full chip Hierarchical Floor Planning, Block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing for Analog-Mixed Signals.
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 Experience in debugging LVS issues at chip-level with complex analog-mixed signal IPs
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 Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption.
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 excellent debugging skills
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 Expertise in FC (Fusion Compiler)
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 Expertise in Primetime, Calibre for DRC/LVS, Ansys Redhawk EMIR
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 Soft Skills &ndash;
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 Should be able to drive decision with cross functional Teams.
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 Good Communication Skills
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 Academic Credentials
 
 
 
 
 
 
 
 Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
 
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Physical Design - Physical Verification Senior Engineer

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Physical Design - Physical Verification Senior Engineer