Qureos Mentor

聯發科技

KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR &lt;-&gt; STA and timely feedbacks to PD team Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure. Generating timing ECO using Tweaker/PrimeClosure.
<br>PREFERRED EXPERIENCE: 5+ years of experience in timing closure of high frequency blocks (&gt; GHz range) Analyzing the timing reports and identifying both design and constraints related issues. Worked on blocks with multiple power and voltage domains Preferred EDA tool experience: Primetime, Tweaker/PrimeClosure, Innovus Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation Strong understanding of SDC constraints, OCV,AOCV,POCV analysis Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering

STA Lead

1. Physical Design Implementation and Methodology: Engage in the implementation of physical design, develop methodologies, and manage sign-off processes. 2. Core Design Tasks: Execute floorplanning, clock planning, placement and routing, timing closure, and physical verification to ensure design integrity and performance. 3. Project Management: Oversee project schedules, troubleshoot design and workflow issues, and drive methodological improvements and execution strategies. 4. Collaborative Teamwork: Work collaboratively with team members to successfully complete projects within designated timelines. 5. Programming Skills: Utilize programming skills to effectively complete tasks, with a focus on scripting and automation to enhance workflow efficiency. 6. Proficiency in EDA Tools: Demonstrate proficiency in using Electronic Design Automation (EDA) tools such as Innovus, ICC2, LEC, PrimeTime, Calibre, among others.
<br>1. Deep Submicron Technology Experience: Hands-on experience with SYN/APR/Signoff and tapeout in deep submicron technology. 2. Familiarity with EDA Tools: Proficient in using EDA tools such as ICC, ICCII, and INNOVUS. 3. ASIC Flow Knowledge: Well-versed in the ASIC design flow. 4. Programming Skills: Proficient in Tcl, Perl, scripting, C, and C++ programming languages. 5. Strong Communication Skills: Excellent communication abilities. 6. Proactive and Responsible: Highly proactive, enthusiastic, and responsible. 7. Education and Experience: MS degree with at least 2 years of experience in the PnR field is preferred. 8. Large-Scale Design Experience: Experience handling designs with more than 2 million instance counts is preferred. 9. Top-Level Physical Design and Advanced Node Experience: Experience in top-level physical design and advanced node tapeout is highly desirable.

PD Engineer (Sr. Staff)

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STA Lead

PD Engineer (Sr. Staff)