About Tessolve
Tessolve offers a unique combination of
design, test, and product engineering
services, enabling our customers to bring products from concept to high-volume production. With a strong presence in semiconductor engineering, we provide a robust environment for growth, learning, and career development.
Job Description
We are looking for a skilled and motivated
Analog Layout Engineer
with 1–3 years of experience in deep sub-micron analog/mixed-signal layout design. The ideal candidate will be responsible for implementing transistor-level layout of analog and mixed-signal blocks while ensuring best practices in layout techniques for matching, parasitic reduction, and reliability.
Job Title:
Analog Layout Engineer
Experience:
1 to 3 Years
Location:
Bangalore
Key Responsibilities
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Ownership of full-custom analog layout blocks from schematics to verified layout.
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Work closely with circuit design engineers to understand requirements and deliver robust layouts.
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Perform layout verification using DRC, LVS, ERC, and PEX tools.
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Support block-level and top-level integration.
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Optimize layout for performance, area, power, and reliability across different PDKs (90nm, 65nm, 28nm, etc.).
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Deliver high-quality GDSII on schedule.
Required Skills & Experience
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1 to 3 years of hands-on experience in analog layout design.
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Strong understanding of analog design fundamentals and layout techniques (matching, shielding, symmetry, etc.).
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Experience in Cadence Virtuoso layout tools and verification tools like Calibre or Assura.
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Good knowledge of CMOS process and parasitic effects.
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Exposure to layout of blocks such as op-amps, bandgap references, data converters, PLLs, LDOs, etc., is a plus.
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Strong communication skills and ability to work collaboratively in a team environment.
Preferred Qualifications
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Bachelor’s/Master’s degree in Electronics, ECE, VLSI, or related discipline.
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Understanding of ESD/Latch-up rules and reliability best practices.
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Experience in scripting (SKILL, Python) is a plus.