Design Verification Engineer

CoMira Solutions is Hiring – Senior Verification/Design Engineer

We’re looking for a hands-on engineer with expertise in digital ASIC verification using SystemVerilog/UVM.

Key Responsibilities:

• Develop and verify RTL design implementations
• Build UVM environments, test benches & verification components
• Plan, implement & analyze functional coverage
• Debug verification environments & recreate field issues
• Work with protocols like Ethernet (802.3), PCIe, CXL, and security algorithms

Requirements:

• 3–5 years of relevant experience
• Strong in SystemVerilog, UVM, scripting (Perl/Python/Shell)
• Familiar with QuestaSim, VCS, or Cadence Incisive
• Bachelors/Masters in Electrical or Computer Engineering

How to Apply: Send your resume to Huma.asif@comira.pk

Job Type: Full-time

Work Location: In person