Digital Verification (DV) Engineer (SI80FT RM 3605)

Position: Digital Verification (DV) (SI80FT RM 3605)

Skills-

Gate level simulations at SOC

Experience in Low Power Simulations

Experience on SoC verification (Co-Sim)

Job Description

10+ Years of experience in Digital Verification.

Should be proficient in System Verilog, UVM and have experience with programming languages such as Perl/Python.

Excellent debugging and analytical skills.

Experience with development of verification plan and verification environment from scratch on multiple projects.

Verification of blocks using System Verilog and UVM including netlist simulation.

Should have worked on assertions, functional coverage, formal verification etc. to reach verification goals.

Interact with the Design Engineers to achieve verification goals.

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