DV- IP verification Engineer (SI18FT RM 3606)

Position: DV- IP verification (SI18FT RM 3606)

Job Description:

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.

1-8 years of experience in design verification, with strong knowledge of verification methodologies (UVM, OVM, etc.).

Proficiency in verification tools (Xrun, VCS, Questa, etc.) and hardware description languages (SystemVerilog, Verilog, etc.).

Experience with FPGA and/or Emulators and embedded Firmware development is an added plus.

Sensitivity : This Document is classified as “LNT General Business & quot

Solid understanding of SoC architecture, including CPU, memory, and peripheral interfaces.

Strong problem-solving skills and the ability to debug complex verification issues.

Proven ability to work effectively in a collaborative team environment.

Experience with scripting languages (Python, Perl, TCL) for automation tasks.

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