Pad Ring Layout Engineer (SI60FF RM 3703)

Position: Pad Ring Layout (SI60FF RM 3703)

JD/expectations below: –

Extensive PAD Ring and Top/Chip level layout experience.

Good understanding of package/substrate design and package assembly rules related to flip chip designs, BGA, LFCSP etc.

Experience in IO Pads, ESD clamps and Analog Mixed Signal IP layout

Layout experience in the following technology nodes is a plus: 180, 40nm and 22nm GF

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