- ASIC
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Location: Bangalore
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Experience: 3 - 5 Years
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B. Tech / M. Tech with hands on experience into Physical verification at block-level& chip-level.
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DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off experience is a must.
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Experience using Synopsys ICC Tool.
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Tape-out experience of multiple complex chips at 14 nm or below is required.
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Experience with Mentor Calibre or Synopsys ICC and ICV is a must.
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Programming experience in tcl, Perl or C.
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Proficient in planning for and addressing electrical considerations throughout the design process (EM, IR, Noise, etc.).
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Physical verification flow automation exposure will be an added advantage.
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com