asic design engineer

Apple

<div>Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next excellent Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple&rsquo;s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a dedicated engineer to join our exciting team of problem solvers. 
 
Description 
 
As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: 
 
<ul><li>Write microarchitecture and/or design specifications</li></ul> 
<ul><li>Design, implement, and debug complex logic designs</li></ul> 
<ul><li>Integrate complex IPs into the SOC</li></ul> 
<ul><li>Support all front end integration activities like Lint, CDC, Synthesis, and ECO</li></ul> 
<ul><li>Work with other specialists that are members of the SOC Design, SOC Design</li></ul> 
<ul><li>Verification, Emulation, STA, and Physical Design teams</li></ul> 
<ul><li>Collaborate with software and systems teams to ensure a high quality</li></ul> 

Preferred Qualifications 
 
Experience writing specifications and converting them to design. 
 
Experience with multiple clock domains and asynchronous interfaces. 
 
Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies 
 
Experience or knowledge of system architecture, CPU &amp; IP Integration, and power and clock management designs desirable. 
 
Ability to communicate optimally across all internal groups 
 
Familiarity with software and operating concepts a plus 
 
Familiarity with scripting languages like Perl, Python, or TCL a plus 
 
Minimum Qualifications 
 
BS and a minimum of 3 years relevant industry experience. 
 
Verilog RTL Logic Design experience. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .</div>

ASIC Design Engineer

<div>Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next excellent Apple product. 
 
Do you enjoy working on challenges that no one has solved yet? As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple&rsquo;s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a dedicated engineer to join our exciting team of problem solvers. 
 
Description 
 
The ideal candidate will have experience in ASIC design with: 
 
<ul><li>Architecture research and/or development of memory or highly interconnected system architectures.</li></ul> 
<ul><li>RTL/micro-architecture.</li></ul> 
<ul><li>Knowledge of high-performance memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram interface calibration/training mechanisms and algorithms is a plus.</li></ul> 
<ul><li>Systems experience in characterizing performance, doing comparison studies, and documenting and publishing results.</li></ul> 

Preferred Qualifications 
 
Drive new memory system architectures from DRAM up. 
 
Explore architecture and feature trade-offs in system performance, area, and power consumption. 
 
Develop memory hierarchies for high performance parallel computer architectures. (system-on-a-chip SOC). 
 
Work with performance team to develop performance/power simulators, models and test suites. 
 
Minimum Qualifications 
 
Bachelor's Degree with +3 Years of Experience. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.</div>

Apple is building the world&rsquo;s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy. 
 
Description 
 
Design and develop hardware for cache subsystem in high performance system on a chip (SoC). 
 
Develop cache micro-architecture based on architecture guidelines and model analysis. 
 
Explore architecture trade-offs in system performance, area, and power consumption. 
 
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem. 
 
Work on front-end netlist and area/timing analysis of the cache subsystem. 
 
Work with physical design team on the timing closure of the cache subsystem. 
 
Preferred Qualifications 
 
Knowledge of high-performance coherent memory systems or interconnect architectures 
 
Knowledge of high-performance DRAM controller 
 
M.S in a relevant field. 
 
Minimum Qualifications 
 
10 + years of full time ASIC design experience 
 
memory system development 
 
RTL/micro-architecture definition 
 
PPA (performance/power/area) analysis 
 
Cache design background including an understanding of different memory organizations and tradeoffs. 
 
Hands on Experience with multi-processor cache coherence protocols 
 
B.S. in a relevant field 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

ASIC Design Engineer - Cache Controller

<div>At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC&rsquo;s for our various products at a rigorous pace. In order to achieve this, Apple&rsquo;s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires knowledge of interconnect fabrics and system memory hierarchy 
 
Description 
 
<ul><li>Design &amp; Integration of coherent and non-coherent fabrics into a subsystem or SoC with good understanding of on-chip interconnect architectures (NoC topologies, crossbars, arbitration).</li></ul> 
<ul><li>Own all aspects of RTL development design, templating, scripting and RTL generation.</li></ul> 
<ul><li>Work and collaborate with other designers in the group to deliver results.</li></ul> 
<ul><li>Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block</li></ul> 
<ul><li>Work with front-end synthesis/STA teams to ensure timing for the block is met</li></ul> 
<ul><li>Work with power/performance and functional verification team to ensure high quality of the block</li></ul> 
<ul><li>Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process</li></ul> 

Preferred Qualifications 
 
Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy. 
 
A consistent track record of delivering large, sophisticated designs in high volume production for low power applications 
 
Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time 
 
Strong interpersonal skills, as the candidate will work with diverse groups within the company 
 
Self-starter, highly motivated, highly organized, and schedule driven 
 
Familiarity with all front-end tools including lint, CDC, synthesis 
 
Minimum Qualifications 
 
Minimum of BS + 3 years relevant industry experience. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .</div>

ASIC Design Engineer - Fabric/Interconnect

Amazon Web Services

<div><h2 class="jobSectionHeader">DESCRIPTION</h2><div>
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. 
 
Key job responsibilities 
As an ASIC Design Engineer, you will: 
 
<ul><li>Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets</li></ul> 
<ul><li>Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements</li></ul> 
<ul><li>Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints</li></ul> 
<ul><li>Execute lint and clock domain crossing quality checks to ensure design integrity</li></ul> 
<ul><li>Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts</li></ul> 
The ideal candidate will have a strong background in ASIC design, proficiency in SystemVerilog, and excellent analytical and problem-solving skills. Experience with high-performance and power-efficient designs is highly desirable. 
 
You will thrive in this role if you: 
<ul><li>Have a &quot;Learn and Be Curious&quot; mindset</li><li>Have familiarity with key components such as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level architectures</li><li>Have a strong drive to innovate, explore new solutions, and contribute to the company's intellectual property through patents</li></ul> 
About the team 
Inclusive Team Culture 
Here at AWS, we embrace our differences. We are committed to furthering our culture of inclusion. We have ten employee-led affinity groups, reaching 40,000 employees in over 190 chapters globally. We have innovative benefit offerings, and host annual and ongoing learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon conferences. Amazon&rsquo;s culture of inclusion is reinforced within our 16 Leadership Principles, which remind team members to seek diverse perspectives, learn and be curious, and earn trust. 
 
Work/Life Balance 
Our team puts a high value on work-life balance. It isn&rsquo;t about how many hours you spend at home or at work; it&rsquo;s about the flow you establish that brings energy to both parts of your life. We believe striking the right balance between your personal and professional life is critical to life-long happiness and fulfillment. We offer flexibility in working hours and encourage you to find your own balance between your work and personal lives. 
 
Mentorship &amp; Career Growth 
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we&rsquo;re building an environment that celebrates knowledge sharing and mentorship. We care about your career growth and strive to assign projects based on what will help each team member develop into a better-rounded professional and enable them to take on more complex tasks in the future.</div><h2 class="jobSectionHeader">
BASIC QUALIFICATIONS</h2><ul><li>Bachelor's degree or equivalent</li><li>3+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience</li></ul><h2 class="jobSectionHeader">
PREFERRED QUALIFICATIONS</h2><ul><li>Master's degree in computer science or equivalent</li><li>3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience</li></ul> 
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. 
 
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. 
 
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner. 
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life &amp; AD&amp;D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits. 
USA, CA, Cupertino - 157,300.00 - 212,800.00 USD annually 
USA, TX, Austin - 136,000.00 - 184,000.00 USD annually</div>

ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration

Apple&rsquo;s Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance and efficiency of Apple&rsquo;s products. You will work on cutting-edge technologies and collaborate with cross-functional teams to deliver groundbreaking solutions. 
 
Description 
 
Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis. 
 
Verification: Engage with simulation-based and formal verification teams to ensure robust design validation. 
 
Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs. 
 
Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals. 
 
Documentation and Reporting: Create detailed micro-architecture and design documentation. 
 
Preferred Qualifications 
 
Educational Background: Bachelor&rsquo;s or Master&rsquo;s degree in Electrical Engineering, Computer Engineering, or a related field. 
 
Experience: 3+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential. 
 
Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis. 
 
Problem-Solving: Strong analytical and problem-solving skills. 
 
Collaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams. 
 
Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs. 
 
Experience with high-speed I/O design and protocols. Knowledge of PCIe is a plus. 
 
Familiarity with custom ASIC design and FPGA prototyping. 
 
Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.). 
 
Knowledge of low-power design techniques and power optimization strategies. 
 
Minimum Qualifications 
 
Minimum of BS + 3 years relevant industry experience 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

ASIC Design and Integration Engineer

<div><h2 class="jobSectionHeader">DESCRIPTION</h2><div>
Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power today's AI workloads across datacenters worldwide. As an ASIC Design Methodologies and Infrastructure Engineer, you'll play a foundational role in the project by automating design flows and building large-scale solutions that accelerate silicon development and we're just getting started here at Amazon! 
 
We're looking for a strong engineer who is passionate about creating design flows and automation flows that enhance both the productivity and quality of our design team. The ideal candidate brings proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving and automating flows. In this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality. 
Key job responsibilities 
 
Core Responsibilities: 
 
<ul><li>Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards.</li><li>Enhance and build design flows to boost the overall productivity of design teams.</li><li>Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.</li></ul> 
About the team 
Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago&mdash;even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help
 
 
Diverse Experiences 
Annapurna values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn&rsquo;t followed a traditional path, or includes alternative experiences, don&rsquo;t let it stop you from applying. 
 
Work/Life Balance 
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there&rsquo;s nothing we can&rsquo;t achieve in the cloud. 
 
Inclusive Team Culture 
Here at Annapurna, it&rsquo;s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon conferences, inspire us to never stop embracing our uniqueness. 
 
Mentorship &amp; Career Growth 
We&rsquo;re continuously raising our performance bar as we strive to become Earth&rsquo;s Best Employer. That&rsquo;s why you&rsquo;ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
</div><h2 class="jobSectionHeader">BASIC QUALIFICATIONS</h2><ul><li>7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience</li><li>7+ years of digital design in communication systems experience</li><li>7+ years of full-custom analog or RF layout experience</li><li>7+ years of wireless communications systems and implementation experience</li><li>8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience</li><li>7+ years of verification in communication systems experience</li><li>5+ years of UVM, C, System C, and scripting experience</li></ul><h2 class="jobSectionHeader">
PREFERRED QUALIFICATIONS</h2><ul><li>Master's degree or Ph.D. degree in Electrical Engineering or related field</li><li>Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs</li><li>Experience with modern ASIC/FPGA design and verification tools</li><li>Experience with SOC bring-up and post-silicon validation</li></ul> 
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. 
 
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. 
 
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner. 
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life &amp; AD&amp;D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits. 
USA, CA, Cupertino - 183,000.00 - 247,600.00 USD annually 
USA, TX, Austin - 159,200.00 - 215,300.00 USD annually</div>

Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

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Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs