asic design engineer

TTM Technologies

<div><p>TTM Technologies, Inc. &ndash; Publicly Traded US Company, NASDAQ (TTMI) &ndash; Top-5 Global Printed Circuit Board Manufacturer
</p><p></p><h2 class="jobSectionHeader"><b>About TTM<br>
</b></h2><p><br>
TTM Technologies, Inc. is a leading global manufacturer of technology products, including mission systems, radio frequency (&ldquo;RF&rdquo;) components, RF microwave/microelectronic assemblies, and technologically advanced printed circuit boards (&ldquo;PCB&rdquo;s). TTM stands for time-to-market, representing how TTM's time-critical, one-stop design, engineering and manufacturing services enable customers to reduce the time required to develop new products and bring them to market.
</p><p></p><p>Additional information can be found at www.ttm.com
</p><p></p><p>Technical leader and group subject matter expert in the area of analog, power management and mixed signal IC development for the CIC (Custom Integrated Circuits) team. Also become the key driver of IC development technical strategy with expert understanding of semiconductor process technologies from fabrication vendors.
</p><p></p><p>Main responsibility will include overseeing definition, design, verification, and documentation for ASIC development. Proven success releasing product to production in the area of analog, power management and mixed signal IC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Significant experience leading the development of multidimensional designs involving the layout of complex integrated circuits, entire active devices, components, sub components and entire subsystems. Utilizes system tools (such as Cadence Virtuoso) for design, simulation, and verification. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Writes the semiconductor specification for an ASIC and performs lab verifications. Also supports the development of the test plan that will be implemented to develop hardware and software for high volume production. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
</p><p></p><p>Tester selection, vendor selection and support the development team to prepare a product to run volume production. The TLSI Engineer main focus includes semiconductor test equipment, software and hardware requirements, test coverage and qualification requirements, analyze statistical results, support RMA (customer returns) and improve test times and yields as needed. Engineering responsibilities associated with new product development or internal R&amp;D efforts. These include design efforts ranging from simple components to complex assemblies driven by customer or internal specifications. Individual works in a multi-disciplinary team environment and is required to participate in proposal efforts and technical reviews.
</p><p></p><ul><li>Drive IC technology strategy and direction.
</li><li>Understand process technology and process selection, preferable from multiple fabrication facilities.
</li><li>Understand customer specifications and drawings to assist in proposal and development efforts.
</li><li>Experience estimating timeframe of design efforts.
</li><li>Work independently or within a team environment. Ensure that project schedules are met.
</li><li>Work with interns, test engineering, and engineering technicians on specific program tasks including test procedure development.
</li><li>Design and evaluate components using available design tools.
</li><li>Follow established standard design process.
</li><li>Understand manufacturing approach and limitations. Perform review before design release.
</li><li>Prepare presentations for gated internal and customer design reviews. Provide nominal simulation results along with tolerances analysis when applicable.
</li><li>Design and evaluate test circuits. Correlate expected performance with test results. Present results in a clear and concise manner.
</li><li>Provide support once design is in production. Support MRB process. Provide reports to customers as needed.
</li><li>Provide training and guidance to interns, co-ops and technicians.
</li></ul><p></p><p><b>KSAs:
</b></p><ul><li>Ability to take ideas and concepts and transform them into producible designs.
</li><li>Ability to design experiments, analyze the data and conduct structured problem solving.
</li><li>Must possess strong written and verbal communication skills to document technical specifications and furnish design review presentations.
</li><li>Strong working knowledge of circuit simulation tools.
</li><li>Strong interpersonal and leadership skills.
</li><li>Strong time management skills. Ability to multitask and prioritize.
</li><li>Strong computer skills, specifically Excel and PowerPoint.
</li><li>Actively pursues opportunities to expand job-related knowledge.
</li><li>Executes on program plans and priorities, identifies obstacles and issues and communicates to achieve resolution for assigned tasks.
</li><li>Ability to interface with customers and work in a multi-disciplinary team environment.
</li></ul><p></p><p><b>Duties and Responsibilities:
</b></p><ul><li>Understand customer specifications and drawings to assist in proposal and development efforts.
</li><li>Experience estimating timeframe of design/layout efforts.
</li><li>Work independently or within a team environment. Ensure that project schedules are met.
</li><li>Provide training and guidance to interns, co-ops and technicians.
</li><li>Layout specific skill-set:
<ul><li>IC Block &amp; Full-Chip Analog/Mixed Signal
</li><li>Floor-planning, Layout, Integration &amp; Verification
</li><li>Cost Analysis Support
</li><li>Cadence Design Systems Tool Suite
</li><li>Virtuoso (Schematic, Layout),
</li><li>PVS, Assura DRC/LVS, QRC Extraction, Voltus Power Analysis
</li><li>Virtuoso Digital Implementation (Encounter/Innovus) P&amp;R
</li><li>Final Signoff &amp; Foundry Tape-out
</li><li>IC Packaging/Test Support
</li></ul></li></ul><p></p><p><b>Education and Experience:
</b></p><ul><li>15yrs. Minimum Relevant Experience
</li><li>Bachelor&rsquo;s, Master&rsquo;s and/or PhD&rsquo;s Degree in Electrical or Electronics Engineering or Related Engineering Discipline with focus on Semiconductor IC design
</li></ul><p></p><p>#LI-VT1<br>
</p><h2 class="jobSectionHeader"><br>
<b><i>Compensation and Benefits:
</i></b></h2><p>TTM offers a variety of health and well-being benefit programs. Benefit options include medical, dental, vision, 401k, flexible spending and health savings accounts, accident benefits, life insurance, disability benefits, paid vacation &amp; holidays. Benefits are available on the 1st of the month following date of hire. For some positions, only PTO and holiday benefits are offered.
</p><p></p><p>Compensation ranges for roles at TTM Technologies varies depending on a wide array of factors that are considered in making compensation decisions including but not limited to skill sets; experience and training; certifications; and other business and organizational needs. The disclosed range estimate has not been adjusted for the applicable geographic differential associated with the location at which the position may be filled. At TTM Technologies, it is not typical for an individual to be hired at or near the top of the range for their role and compensation decisions are dependent on each individual set of circumstances. A reasonable estimate of the current range is:
</p>$156,102 - $274,525
<p></p><p>Additional compensation: An annual or quarterly company bonus may apply based on position assignment. Positions hired for alternative shift may be eligible for a shift premium based on the assigned shift and location.
</p><p></p><p><b><i>Export Statement:
</i></b><br>
Must comply with TTM Export Control Policies and Procedures and all applicable laws including ITAR, EAR and OFAC including but not limited to: a) being able to identify ITAR product on the manufacturing floor and understand that access to these products and related technical data is restricted to only US Citizens and US Permanent Residents; b) recognition of Foreign Person visitors by badge differentiation; c) understand and follow authorization procedures for bringing foreign visitors into facilities (VAL); d) understand the Export and ITAR requirements for shipments leaving the US; e) manage vendor approvals for ITAR manufacturing and services.
</p><p>All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.</p></div>

Principal ASIC Design Engineer

Teradyne

<div><p>We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!</p><p></p><p><br>
We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.</p><p></p><p><b><br>
Our Purpose</b><br>
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.<br>
<br>
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team &ndash; one that makes better decisions, drives innovation and delivers better business results.</p><p><b><br>
Opportunity Overview</b></p><p>
Our Hardware Engineering team is seeking an FPGA/ASIC Design Engineer to work with a multi-disciplined team to design, code, and verify FPGAs in our cutting-edge products in a fast-paced, process-oriented environment.
</p><ul><li>Deriving requirements from higher level specifications</li><li>
Writing design documents</li><li>
Designing and implementing register-transfer-level (RTL) code using Verilog</li><li>
Designing with Vendor IPs and various industry standard interface protocols</li><li>
Use of digital simulation tools to verify designs.</li><li>
Creation of physical design constraints for placement, timing closure and CDC</li><li>
Implementation of designs into target technologies using synthesis and place and route tools</li><li>
Perform timing analysis using static timing analysis tools.</li><li>
Perform lab debug of designs with laboratory equipment such as Logic Analyzers and oscilloscopes.</li><li>
Collaboration with other logic designers, board designers, software designers and ASIC designers</li><li>
Communicating status to project leadership</li></ul><p></p><p><b><br>
All About You</b><br>
We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you&rsquo;re ready to join us in this mission, take a closer look at the minimum criteria for the position.</p><ul><li>
BS/MS in Electrical Engineering</li><li>
Minimum of 2+ years of industry experience</li><li>
Knowledgeable in digital logic design</li><li>
Experience in logic design writing RTL in Verilog HDL</li><li>
Familiarity with a scripting language such as Python, TCL and Perl</li><li>
Experience with physical design tools from FPGA vendors (Vivado or Quartus) or ASIC vendors.</li><li>
Ability to debug difficult problems using a variety of software and hardware tools (debugger, JTAG emulator, logic analyzer, and oscilloscope)</li><li>
Highly motivated, team player, willing to pick up any piece of code, with a can-do attitude, and attracted to challenging opportunities</li><li>
Excellent written and oral communication skills</li><li>
Familiarity with high-speed serial protocols including PCIe and Ethernet.</li><li>
Familiarity with a digital simulation tool such as Synopsys, Cadence, or Mentor</li><li>
High Speed digital circuit design</li><li>
Familiarity with C/C++</li><li>
Familiarity in the use of a source control tools</li><li>
Familiarity working in a Linux based development environment</li></ul><p></p><p><i><br>
This position is not eligible for visa sponsorship</i></p><p></p><p><b><br>
Compensation:</b><br>
The base salary range for this role is $97,900- 156,700. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.</p><p><br>
</p><p><b>Incentive Plan: </b>This job is eligible for discretionary bonus(es) based on financial performance.</p><p></p><p><b><br>
Benefits:</b></p><p>
Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation &amp; holidays, tuition assistance programs, and more. Please click here to see details.</p><p></p><p><br>
#LI-NS1</p></div>

ASIC/FPGA Design Engineer (Compute Test Division; North Reading, MA)

Marvell Technology

<div><div>About Marvell</div><div>
Marvell&rsquo;s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.</div><div></div><div>
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.</div><div></div><div>
Your Team, Your Impact</div><div></div>
As a Digital IC Design Principal Engineer with Marvell, you&rsquo;ll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that drive high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues.<div></div><div>
What You Can Expect</div><div>
The position will be responsible for implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs. The work will involve running Tessent tools for insertion of all DFT structures. The role will involve chiplet DFT solutions, will include Tessent SSN, and will require strong verification and debug skills.</div><ul><li>
The engineer will need to show proficiency in ICL/PDL, PTAP/STAP, 1687. It is a requirement that the engineer is knowledgeable in instrument-level access inside a chip.</li><li>
The engineer will work with other leads to help with Design-for-Test architecture definition and implementation of additional DFT/DFX features</li><li>
The engineer will also be involved in STA constraint definition, pattern generation &amp; post-silicon bring-up and debug.</li><li>
In this position, the responsibility will grow to include mentoring, guiding and driving a small team of DFT engineers.</li><li>
The engineer will work with other leads to help enhance DFT methodologies and tools.</li></ul><div></div><div>
What We're Looking For</div><ul><li>
Bachelor&rsquo;s, Master&rsquo;s degree or PhD in Computer Science, Electrical Engineering or related fields with minimum of 10 years of work experience.</li><li>
Direct DFT experience with at least 8 years in the custom chip (ASIC) design business</li><li>
Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug</li><li>
Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design.</li><li>
Strong fundamentals in digital circuit design and logic design</li><li>
Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC), with Tessent the EDA tool flow in use.</li><li>
Proven track record of problem solving and innovation to meet challenging design requirements.</li><li>
Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion.</li><li>
Excellent communications skills both verbal and written.</li><li>
Scripting skills using Python, PERL, Tcl and C-Shell is plus.</li></ul><div></div><div>
Expected Base Pay Range (USD)</div>
184,400 - 272,950, $ per annum<div></div><div>
The successful candidate&rsquo;s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.</div><div></div><div>
Additional Compensation and Benefit Elements</div>
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life&rsquo;s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.<div></div><div>
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.</div><div></div><div>
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at <div>TAOps@marvell.com</div>.</div><div></div><div>
Interview Integrity</div><div>
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.</div><div></div><div>
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.</div><div></div><div>
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.</div><div></div>
#LI-NF1</div>

Principal Engineer - Design For Test (DFT)

Amazon.com

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><p>
Amazon Leo is Amazon&rsquo;s low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity.<br>
<br>
Export Control Requirement:<br>
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.<br>
<br>
This is a full-time position, meaning candidates should expect to work in office, Monday-Friday, up to 40 hours per week typically between 8am-5pm. Specific team norms around working hours will be communicated by your manager.<br>
<br>
NOTE: By applying to this position, your application will be considered for all Application-Specific Integrated Circuit roles at all locations we hire for in the United States including but not limited to: Greater Seattle Area (Seattle, Bellevue, Redmond), Greater Bay Area (San Francisco, Sunnyvale, Santa Clara), Greater DMV (DC, MD, VA), Austin (TX), New York City (NY), Minneapolis (MN).<br>
<br>
At Amazon, we hire the best minds in technology to innovate and build on behalf of our customers. The intense focus we have on our customers is why we are one of the world&rsquo;s most beloved brands. Customer obsession is part of our company DNA.<br>
<br>
As part of a project team you will work alongside Senior ASIC Engineers; supporting the design, debug, validation and optimization of the products. You will be involved in projects from concept through production, gaining exposure to the complete design lifecycle. You will also support engineering builds gaining experience with high volume manufacturing. Some positions may require international travel.<br>
<br>
Key job responsibilities<br>
As an ASIC Engineer you will engage with an experienced cross-disciplinary staff to conceive and design innovative consumer products. You will work closely with an internal inter-disciplinary team, and outside partners to drive key aspects of product definition, execution, and verification. You must be responsive, flexible and able to succeed within an open collaborative peer environment.<br>
Responsibilities:<br>
Participate in logic design, verification and post-silicon validation as part of Amazon custom silicon solutions.<br>
Work with physical design teams to achieve performance and area requirements.<br>
Develop a deep understanding of the end customer requirements, including software applications, use models, system architecture and the SoC architecture/micro-architecture of our solutions.<br>
Develop and execute design automation mechanisms and flows.<br>
<br>
A day in the life<br>
We&rsquo;re on the lookout for the curious, those who think big and want to define the world of tomorrow.<br>
At Amazon, you will grow into the high impact, visionary person you know you&rsquo;re ready to be. Every day will be filled with exciting new challenges, developing new skills, and achieving personal growth.<br>
How often can you say that your work changes the world? At Amazon, you&rsquo;ll say it often. Join us and define tomorrow.</p><h2 class="jobSectionHeader"><b>
BASIC QUALIFICATIONS</b></h2><ul><li>Currently has, or is in the process of obtaining, a Bachelor's degree or above in Electrical Engineering, Computer Engineering, or related fields</li><li>Experience troubleshooting and debugging technical systems, or experience demonstrating software engineering skills in a previous intership, work experience, coding competitions, or publications and experience that includes strong analytical skills, attention to detail, and effective communication abilities</li><li>Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs</li><li>Experience in C/C++ and system Verilog coding</li><li>Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area</li><li>Experience with modern ASIC/FPGA design and verification tools</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Experience that includes strong analytical skills, attention to detail, and effective communication abilities</li></ul><br>
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.<br>
<br>
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.<br>
<br>
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.<p><br>
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life &amp; AD&amp;D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.</p><br>
USA, CA, SAN DIEGO - 122,600.00 - 170,000.00 USD annually<br>
USA, CA, San Diego - 122,600.00 - 170,000.00 USD annually<br>
USA, CA, Sunnyvale - 126,100.00 - 185,000.00 USD annually<br>
USA, TX, AUSTIN - 109,700.00 - 160,000.00 USD annually<br>
USA, TX, Austin - 109,700.00 - 160,000.00 USD annually<br>
USA, WA, Redmond - 109,700.00 - 160,000.00 USD annually</div><p></p>

ASIC Engineer, Project Leo

Microchip Technology

<div><div>Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.</div><div></div><div>
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip&rsquo;s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our <div>Vision, Mission, and 11 Guiding Values</div>; we affectionately refer to it as the <i>Aggregate System</i> and it&rsquo;s won us countless awards for diversity and workplace excellence.</div><div></div><div>
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over <div>30 years of quarterly profitability</div> without a great team dedicated to empowering innovation. People like you.</div><div></div><div>
Visit our <div>careers</div> page to see what exciting opportunities and company <div>perks</div> await!</div><div></div><div>
Job Description:</div><div></div><div>
You will be working with our Design team in FPGA -BU working from our Hyderabad Design centre. The work involves Timing closure of various ASIC blocks at block level as well as at Full chip level. develop STA environment for industry standard STA signoff tools like Primetime and Tempus. You will develop and execute several STA testcases intended to catch timing violations. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures at block level as well as full chip level, to develop constraints and, debug the setup, performs timing and analyse Timing violations.</div><div>
You will work closely with design engineers, custom engineers and layout engineers to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills is a must.</div><div></div><div>
Requirements/Qualifications:</div><div></div><ul><li> Perform Static Timing Analysis ASIC blocks and full chip with industry lead EDA tools like prime-time/Tempus understand different interfaces, ASIC blocks and work on constraints and develop different STA modes at block level and full chip level.</li><li> Track post layout netlist releases spef extractions and integrate the new releases into full chip STA environment.</li><li> Good understanding of various timing models used for STA</li><li> Perform verification processes with modelling and simulation using industry standard simulators &bull; Maintain technical expertise and provide training to juniors</li><li> Contribute to cross group communication to work towards standardization and group success</li><li> Proactively solicit input from Standards, CAD, modelling and layout to ensure the design quality</li><li> Previous strong experience in STA and writing timing constrains is must.</li><li> Experience in taking an industrial standards/specification and implementing the IP blocks / RTL design and integration is added advantage.</li><li> Good understanding on timing/area/power/complexity trade-offs on complex interface design</li><li> Experience in frontend implementation tasks such as synthesis and logic equivalence is advantage</li><li> Experience in large scale mix signal circuitry design including logic implementation/verification, timing analysis/optimization an advantage</li><li> Excellent problem-solving and analytical skills. A self-motivated, enthusiastic team player who enjoys working with others.</li><li> Good communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form is must.</li><li> Experience of 3 to 4 years.</li></ul><div></div><div>
Travel Time:</div><div></div>
No Travel<div></div><div>
To all recruitment agencies: <i>Microchip Technology Inc. </i><i>does not</i><i> accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.</i></div></div>

Engineer II - STA

Cisco

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.
<br><br>
Meet the team
<br><br>
Join the Cisco Common ASIC Group—a passionate, world-class team pioneering the future of programmable, high-speed switching solutions. Our team’s mission is to accelerate innovation by enabling early detection of performance and functional issues in ASICs, ensuring reliable and scalable network infrastructure. As a diverse and highly collaborative group, we blend expertise in hardware, software, and emulation to deliver the backbone of global data connectivity. With a culture rooted in technical excellence and continuous learning, we’re excited to build tomorrow’s switching systems that power the world’s internet experiences. Be part of a unique team whose solutions touch nearly every internet transaction globally.
<br><br>
Your impact
<br><br>
Drive the development of advanced ASIC emulation environments to accelerate pre-silicon validation and improve time-to-market for next-generation switching systems. Build and refine emulation infrastructure using C/C++ and TCL, enabling early identification of critical issues and enabling robust silicon. Collaborate closely with design, verification, power, and diagnostic teams to implement, test, and debug complex multi-terabit systems. Develop and execute sophisticated test plans and traffic scenarios to ensure flawless system performance post-silicon. Shape the reliability and scalability of the hardware that underpins cloud and enterprise networks worldwide.
<br><br>
Minimum qualifications
<br><br>
<ul>
<li>Master’s degree in Electrical Engineering, Electronics Engineering, or Computer Engineering with 4+ years of relevant experience, OR Bachelor’s degree in the same fields with 5+ years of relevant experience</li>
<li>2+ years of emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation, debug, performance testing.</li>
<li>Proficiency in RTL development using Verilog or System Verilog for emulation prototypes</li>
<li>Proficiency in C/C++ and TCL for emulation infrastructure development</li>
<li>Experience with system debug tools (e.g., gdb, waveform debuggers)</li>
</ul>
Preferred qualifications
<br><br>
<ul>
<li>Experience with scripting languages (e.g., Python, Perl)</li>
<li>Strong written and verbal communication skills</li>
<li>Post-silicon functional validation or debugging experience</li>
<li>Knowledge of protocols such as PCIe, I2C, Ethernet packet headers, and Ethernet protocol</li>
<li>Collaborative mindset with a drive to learn and contribute in a team environment</li>
</ul>
Why Cisco?
<br><br>
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
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<br>We are Cisco, and our power starts with you.

Emulation Engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
SOC PERFORMANCE MODELING ENGINEER</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
The successful candidate will work in AMD's Client Performance Modeling Team in Hyderabad, India. The team&rsquo;s mandate is to analyze the architectural performance of notebook and desktop processors through modeling and RTL simulation. This role will involve working with SoC, IP &amp; Model architects to evaluate and debug CPU/GFX/NPU processor performance and propose architectural enhancements.</div><div></div><div><b><br>
THE PERSON:</b></div><div>
You have a passion for leading edge SoC architecture, digital design and verification. You are a team player who has excellent communication skills and enjoys collaborating with architects &amp; engineers located in different sites and time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Develop architectural models, tools and infrastructure</li><li>
Investigate performance features, optimize settings</li><li>
Propose/evaluate improvements for next gen SOCs</li><li>
Carry out feature perf/power/area trade-off studies</li><li>
Evaluate CPU, GFX, NPU benchmarks to address performance bottlenecks</li><li>
Drive simulation infrastructure and methodology advances</li><li>
Provide technical guidance and recommendations to Client SoC team</li></ul><div></div><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
8-15years of prior industry/academic experience</li><li>
Experience with computer system simulation and performance evaluation</li><li>
Experience with ASIC HW design and verification languages/tools (Verilog, System Verilog, System C, OVM/OVC)</li><li>
Proficiency with programming and scripting languages (C/C++, Perl, Python, etc.)</li><li>
Experience analyzing system bottlenecks and optimizing computing systems for performance</li><li>
Detailed microarchitecture knowledge of a CPU, GPU, NPU, I/O subsystem, and/or DRAM controller</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in Computer/Electrical Engineering</li></ul><p></p><p><br>
#LI-PK2</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div><div></div><div><i><br>
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available </i><i>here.</i></div><div></div><div><i><br>
This posting is for an existing vacancy.</i></div></div>

SOC Performance Modelling- CPU Architecture

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