asic engineer

Amazon.com

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><p>
Amazon Leo is Amazon&rsquo;s low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity.<br>
<br>
Export Control Requirement:<br>
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.<br>
<br>
This is a full-time position, meaning candidates should expect to work in office, Monday-Friday, up to 40 hours per week typically between 8am-5pm. Specific team norms around working hours will be communicated by your manager.<br>
<br>
NOTE: By applying to this position, your application will be considered for all Application-Specific Integrated Circuit roles at all locations we hire for in the United States including but not limited to: Greater Seattle Area (Seattle, Bellevue, Redmond), Greater Bay Area (San Francisco, Sunnyvale, Santa Clara), Greater DMV (DC, MD, VA), Austin (TX), New York City (NY), Minneapolis (MN).<br>
<br>
At Amazon, we hire the best minds in technology to innovate and build on behalf of our customers. The intense focus we have on our customers is why we are one of the world&rsquo;s most beloved brands. Customer obsession is part of our company DNA.<br>
<br>
As part of a project team you will work alongside Senior ASIC Engineers; supporting the design, debug, validation and optimization of the products. You will be involved in projects from concept through production, gaining exposure to the complete design lifecycle. You will also support engineering builds gaining experience with high volume manufacturing. Some positions may require international travel.<br>
<br>
Key job responsibilities<br>
As an ASIC Engineer you will engage with an experienced cross-disciplinary staff to conceive and design innovative consumer products. You will work closely with an internal inter-disciplinary team, and outside partners to drive key aspects of product definition, execution, and verification. You must be responsive, flexible and able to succeed within an open collaborative peer environment.<br>
Responsibilities:<br>
Participate in logic design, verification and post-silicon validation as part of Amazon custom silicon solutions.<br>
Work with physical design teams to achieve performance and area requirements.<br>
Develop a deep understanding of the end customer requirements, including software applications, use models, system architecture and the SoC architecture/micro-architecture of our solutions.<br>
Develop and execute design automation mechanisms and flows.<br>
<br>
A day in the life<br>
We&rsquo;re on the lookout for the curious, those who think big and want to define the world of tomorrow.<br>
At Amazon, you will grow into the high impact, visionary person you know you&rsquo;re ready to be. Every day will be filled with exciting new challenges, developing new skills, and achieving personal growth.<br>
How often can you say that your work changes the world? At Amazon, you&rsquo;ll say it often. Join us and define tomorrow.</p><h2 class="jobSectionHeader"><b>
BASIC QUALIFICATIONS</b></h2><ul><li>Currently has, or is in the process of obtaining, a Bachelor's degree or above in Electrical Engineering, Computer Engineering, or related fields</li><li>Experience troubleshooting and debugging technical systems, or experience demonstrating software engineering skills in a previous intership, work experience, coding competitions, or publications and experience that includes strong analytical skills, attention to detail, and effective communication abilities</li><li>Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs</li><li>Experience in C/C++ and system Verilog coding</li><li>Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area</li><li>Experience with modern ASIC/FPGA design and verification tools</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Experience that includes strong analytical skills, attention to detail, and effective communication abilities</li></ul><br>
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.<br>
<br>
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.<br>
<br>
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.<p><br>
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life &amp; AD&amp;D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.</p><br>
USA, CA, SAN DIEGO - 122,600.00 - 170,000.00 USD annually<br>
USA, CA, San Diego - 122,600.00 - 170,000.00 USD annually<br>
USA, CA, Sunnyvale - 126,100.00 - 185,000.00 USD annually<br>
USA, TX, AUSTIN - 109,700.00 - 160,000.00 USD annually<br>
USA, TX, Austin - 109,700.00 - 160,000.00 USD annually<br>
USA, WA, Redmond - 109,700.00 - 160,000.00 USD annually</div><p></p>

ASIC Engineer, Project Leo

Cisco

Meet the Team
<br><br>
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With 2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
<br><br>
Your Impact
<br><br>
<ul>
<li>Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.</li>
<li>Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.</li>
<li>Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.</li>
<li>The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.</li>
</ul>
You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of technologies.
<br><br>
<b>Minimum Qualifications:</b><br>
<ul>
<li>Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 4-6 years of experience.</li>
<li>Knowledge of the latest innovative trends in DFT, test and silicon engineering.</li>
<li>Experience with Jtag protocols, Scan insertion and ATPG.</li>
<li>Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.</li>
<li>Knowledge of the latest innovative trends in DFT, test and silicon engineering.</li>
<li>Experience working with Gate level simulation, debugging with VCS and other simulators.</li>
<li>Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687</li>
<li>Strong verbal skills and ability to thrive in a multifaceted environment</li>
<li>Scripting skills: Tcl, Python/Perl.</li>
</ul>
<b>Preferred Qualifications:</b><br>
<ul>
<li>Test Static Timing Analysis</li>
<li>Post silicon validation using DFT patterns.</li>
</ul>
Why Cisco?
<br><br>
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
<br>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
<br>We are Cisco, and our power starts with you.

ASIC DFT Engineer

TTM Technologies

<div><p>TTM Technologies, Inc. &ndash; Publicly Traded US Company, NASDAQ (TTMI) &ndash; Top-5 Global Printed Circuit Board Manufacturer
</p><p></p><h2 class="jobSectionHeader"><b>About TTM<br>
</b></h2><p><br>
TTM Technologies, Inc. is a leading global manufacturer of technology products, including mission systems, radio frequency (&ldquo;RF&rdquo;) components, RF microwave/microelectronic assemblies, and technologically advanced printed circuit boards (&ldquo;PCB&rdquo;s). TTM stands for time-to-market, representing how TTM's time-critical, one-stop design, engineering and manufacturing services enable customers to reduce the time required to develop new products and bring them to market.
</p><p></p><p>Additional information can be found at www.ttm.com
</p><p></p><p>Technical leader and group subject matter expert in the area of analog, power management and mixed signal IC development for the CIC (Custom Integrated Circuits) team. Also become the key driver of IC development technical strategy with expert understanding of semiconductor process technologies from fabrication vendors.
</p><p></p><p>Main responsibility will include overseeing definition, design, verification, and documentation for ASIC development. Proven success releasing product to production in the area of analog, power management and mixed signal IC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Significant experience leading the development of multidimensional designs involving the layout of complex integrated circuits, entire active devices, components, sub components and entire subsystems. Utilizes system tools (such as Cadence Virtuoso) for design, simulation, and verification. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Writes the semiconductor specification for an ASIC and performs lab verifications. Also supports the development of the test plan that will be implemented to develop hardware and software for high volume production. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
</p><p></p><p>Tester selection, vendor selection and support the development team to prepare a product to run volume production. The TLSI Engineer main focus includes semiconductor test equipment, software and hardware requirements, test coverage and qualification requirements, analyze statistical results, support RMA (customer returns) and improve test times and yields as needed. Engineering responsibilities associated with new product development or internal R&amp;D efforts. These include design efforts ranging from simple components to complex assemblies driven by customer or internal specifications. Individual works in a multi-disciplinary team environment and is required to participate in proposal efforts and technical reviews.
</p><p></p><ul><li>Drive IC technology strategy and direction.
</li><li>Understand process technology and process selection, preferable from multiple fabrication facilities.
</li><li>Understand customer specifications and drawings to assist in proposal and development efforts.
</li><li>Experience estimating timeframe of design efforts.
</li><li>Work independently or within a team environment. Ensure that project schedules are met.
</li><li>Work with interns, test engineering, and engineering technicians on specific program tasks including test procedure development.
</li><li>Design and evaluate components using available design tools.
</li><li>Follow established standard design process.
</li><li>Understand manufacturing approach and limitations. Perform review before design release.
</li><li>Prepare presentations for gated internal and customer design reviews. Provide nominal simulation results along with tolerances analysis when applicable.
</li><li>Design and evaluate test circuits. Correlate expected performance with test results. Present results in a clear and concise manner.
</li><li>Provide support once design is in production. Support MRB process. Provide reports to customers as needed.
</li><li>Provide training and guidance to interns, co-ops and technicians.
</li></ul><p></p><p><b>KSAs:
</b></p><ul><li>Ability to take ideas and concepts and transform them into producible designs.
</li><li>Ability to design experiments, analyze the data and conduct structured problem solving.
</li><li>Must possess strong written and verbal communication skills to document technical specifications and furnish design review presentations.
</li><li>Strong working knowledge of circuit simulation tools.
</li><li>Strong interpersonal and leadership skills.
</li><li>Strong time management skills. Ability to multitask and prioritize.
</li><li>Strong computer skills, specifically Excel and PowerPoint.
</li><li>Actively pursues opportunities to expand job-related knowledge.
</li><li>Executes on program plans and priorities, identifies obstacles and issues and communicates to achieve resolution for assigned tasks.
</li><li>Ability to interface with customers and work in a multi-disciplinary team environment.
</li></ul><p></p><p><b>Duties and Responsibilities:
</b></p><ul><li>Understand customer specifications and drawings to assist in proposal and development efforts.
</li><li>Experience estimating timeframe of design/layout efforts.
</li><li>Work independently or within a team environment. Ensure that project schedules are met.
</li><li>Provide training and guidance to interns, co-ops and technicians.
</li><li>Layout specific skill-set:
<ul><li>IC Block &amp; Full-Chip Analog/Mixed Signal
</li><li>Floor-planning, Layout, Integration &amp; Verification
</li><li>Cost Analysis Support
</li><li>Cadence Design Systems Tool Suite
</li><li>Virtuoso (Schematic, Layout),
</li><li>PVS, Assura DRC/LVS, QRC Extraction, Voltus Power Analysis
</li><li>Virtuoso Digital Implementation (Encounter/Innovus) P&amp;R
</li><li>Final Signoff &amp; Foundry Tape-out
</li><li>IC Packaging/Test Support
</li></ul></li></ul><p></p><p><b>Education and Experience:
</b></p><ul><li>15yrs. Minimum Relevant Experience
</li><li>Bachelor&rsquo;s, Master&rsquo;s and/or PhD&rsquo;s Degree in Electrical or Electronics Engineering or Related Engineering Discipline with focus on Semiconductor IC design
</li></ul><p></p><p>#LI-VT1<br>
</p><h2 class="jobSectionHeader"><br>
<b><i>Compensation and Benefits:
</i></b></h2><p>TTM offers a variety of health and well-being benefit programs. Benefit options include medical, dental, vision, 401k, flexible spending and health savings accounts, accident benefits, life insurance, disability benefits, paid vacation &amp; holidays. Benefits are available on the 1st of the month following date of hire. For some positions, only PTO and holiday benefits are offered.
</p><p></p><p>Compensation ranges for roles at TTM Technologies varies depending on a wide array of factors that are considered in making compensation decisions including but not limited to skill sets; experience and training; certifications; and other business and organizational needs. The disclosed range estimate has not been adjusted for the applicable geographic differential associated with the location at which the position may be filled. At TTM Technologies, it is not typical for an individual to be hired at or near the top of the range for their role and compensation decisions are dependent on each individual set of circumstances. A reasonable estimate of the current range is:
</p>$156,102 - $274,525
<p></p><p>Additional compensation: An annual or quarterly company bonus may apply based on position assignment. Positions hired for alternative shift may be eligible for a shift premium based on the assigned shift and location.
</p><p></p><p><b><i>Export Statement:
</i></b><br>
Must comply with TTM Export Control Policies and Procedures and all applicable laws including ITAR, EAR and OFAC including but not limited to: a) being able to identify ITAR product on the manufacturing floor and understand that access to these products and related technical data is restricted to only US Citizens and US Permanent Residents; b) recognition of Foreign Person visitors by badge differentiation; c) understand and follow authorization procedures for bringing foreign visitors into facilities (VAL); d) understand the Export and ITAR requirements for shipments leaving the US; e) manage vendor approvals for ITAR manufacturing and services.
</p><p>All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.</p></div>

Principal ASIC Design Engineer

Swedium Global Services Pvt Ltd

<p>Greeting from Swedium Global Services.</p><p>We have an immediate opportunity for Senior DFT Engineer.</p><p>JD :</p><p>Experience-7+ Years</p><p>Expected Start date: ASAP</p><p>Location- Onsite in Bangalore -5 Days of office</p><p>Job Name: DFT Engineer-ASIC</p><p>Job Summary</p><p>We are seeking a DFT Engineer to join our ASIC design team to develop and implement design-for-test methodologies for complex SoCs. The DFT engineer will be responsible for scan insertion, BIST implementation, ATPG pattern generation, and test coverage analysis to ensure high-quality, testable silicon.</p><p>Key Responsibilities</p><ul><li>Develop and implement DFT architecture for ASIC/SoC designs in collaboration with front-end and back-end design teams.</li><li>Insert and verify scan chains, boundary scan (JTAG), MBIST, and LBIST structures at RTL or gate level.</li><li>Perform ATPG pattern generation for stuck-at, transition, and path delay faults; analyze and improve test coverage.</li><li>Plan and integrate test compression and diagnostic features to reduce test time and cost.</li><li>Ensure DFT rule compliance throughout the synthesis and implementation flow.</li><li>Collaborate with the physical design team for DFT constraint setup, timing closure, and test mode verification.</li><li>Support silicon bring-up, pattern validation, and failure debug during post-silicon testing.</li><li>Maintain DFT scripts and automation for improved efficiency and consistency across projects.</li><li>Work with ATE (Automated Test Equipment) engineers to ensure smooth pattern transfer and test execution.</li><li>Document DFT methodologies, coverage metrics, and sign-off reports.</li></ul><p>Required Qualifications</p><ul><li>Bachelor&rsquo;s or Master&rsquo;s degree in Electrical Engineering, Electronics, or a related field.</li><li>7+ years of hands-on experience in ASIC/SoC DFT implementation.</li><li>Strong understanding of:</li><li>Scan insertion and scan architecture</li><li>ATPG (stuck-at, transition faults)</li><li>MBIST/LBIST methodologies</li><li>Boundary scan (IEEE 1149.1)</li><li>Proficiency in DFT EDA tools, such as:</li><li>Synopsys DFT Compiler, TetraMAX / TestMAX</li><li>Siemens (Mentor) Tessent</li><li>Cadence Modus</li><li>Solid understanding of ASIC design flow &mdash; synthesis, timing, verification, and P&amp;R.</li><li>Working knowledge of Verilog/SystemVerilog and scripting languages (TCL, Perl, Python, or Shell).</li><li>Familiarity with ATE testing concepts and pattern debug.</li><li>Excellent problem-solving, analytical, and communication skills.</li></ul><p>If anyone interested in this assignment, kindly reach out to akshatha.mogerti@swediumglobal.com &amp; 8197100437.</p><p>Job Types: Full-time, Permanent</p><p>Pay: Up to ₹3,500,000.00 per year</p><p>Benefits:</p><ul><li>Cell phone reimbursement</li><li>Health insurance</li><li>Provident Fund</li></ul><p>Work Location: In person</p>

Senior DFT Engineer

Siliciom Technologies

<div></div><div><div><div><ul><li>ASIC</li><li>
Location: Bangalore</li><li>
Experience: 1 - 5 Years</li></ul><h5 class="jobSectionHeader"><b>
Required Skills &amp; Knowledge:</b></h5><ul><li>
BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE</li><li>
Design and develop test benches using HVLs like System Verilog</li><li>
Deep expertise in Verification Methodologies like OVM, UVM</li><li>
Should have experience in creating verification environment and test plans</li><li>
Domain expertise either Networking protocols / Interface protocols</li><li>
like PCIe, USB, DDR, MIPI, AXI, SATA / SoC Verification is essential</li><li>
Familiarity with Scripting languages</li><li>
Good written and communication skills.</li></ul><p>
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com</p></div></div></div>

Verification Engineer:

<div></div><div><div><div><ul><li>ASIC</li><li>
Location: Bangalore</li><li>
Experience: 3 - 5 Years</li></ul><h5 class="jobSectionHeader"><b>
Required Skills &amp; Knowledge:</b></h5><ul><li>
Btech/Mtech Electronics/Electrical engineering</li><li>
Experience in Analog Mixed-signal layout and verification of high-speed digital and/or DDR IOs, Critical signal inclusion.</li><li>
Advanced understanding of Deep submicron effects and mitigation.</li><li>
Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies.</li><li>
Solid understanding of CMOS and FinFETlayouts and process technology in 28nm and smaller.</li><li>
Good understanding of basic ESD and latchup layout design considerations.</li><li>
Familiarity with ASIC physical design flow:LEF generation, Place &amp; Route &amp; understanding of top level verification flow, DRC/LVS, LPE.</li><li>
Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc</li><li>
Scripting skills for layout automation is a plus</li><li>
emote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership.</li><li>
Excellent written and verbal communication skills in interactions with customers, and internal development teams.</li></ul><p>
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com</p></div></div></div>

Analog Layout Engineer:

<div></div><div><div><div><ul><li>ASIC</li><li>
Location: Bangalore</li><li>
Experience: 1 - 5 Years</li></ul><h5 class="jobSectionHeader"><b>
Required Skills &amp; Knowledge:</b></h5><ul><li>
B.E/M.E/M.Tech or B.S/M.S in EE/CE.</li><li>
Responsibilities include RTL development, resolving system level challenges.</li><li>
Architecting, implementing, documenting and validating the memory controller IP cores.</li><li>
Candidate must have excellent Verilog and SystemVerilog concepts.</li><li>
Experience in verification of complex RTL designs and validating them on the boards is an added advantage.</li><li>
Working knowledge of UNIX environment and scripting languages (PERL, Python/TCL etc) desired.</li><li>
Knowledge of AXI/AHB AMBA bus based complex multi-master &amp; slave systems.</li><li>
Good waveform debug skills using front end industry standard design tools like VCS, NCSIM and Questa.</li><li>
Expertise with FPGA architecture and Xilinx implementation tools (Vivado) highly desired.</li><li>
Excellent communication and problem solving skills.</li></ul><p>
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com</p></div></div></div>

RTL Design Engineer:

Search 7019+ Asic engineer jobs near you this March. New roles added regularly across leading industries. Apply today.