asic verification engineer

Qualcomm

<div><h2 class="jobSectionHeader"><b>Company:</b></h2>
Qualcomm Technologies, Inc.<p></p><h2 class="jobSectionHeader"><b>
Job Area:</b></h2>
Engineering Group, Engineering Group &gt; ASICS Engineering<p></p><p><b>
General Summary:</b></p><p>
Qualcomm Technologies Inc's Global CAD team develops tools, flows, and methodologies for different aspects of VLSI design. This position is about developing critical CAD tools used in emulation and includes the following activities:</p><p></p><ul><li>
Work with industry-standard tools and technologies to develop solutions to a variety of infrastructure needs.</li><li>
Develop critical emulation CAD algorithms that address unique Qualcomm SoC needs (synthesis, partitioning, place and route, clock optimization).</li><li>
Drive compute and storage optimization.</li><li>
Mentor and lead other members of the team</li></ul><p></p><p><b>
Qualifications:</b></p><ul><li>
Bachelor's degree in Science, Engineering, or related field.</li><li>
7+ years ASIC design, FPAG design, verification, or related work experience.</li><li>
7+ years C++ SW development, CAD tool development, or related work experience.</li></ul><p></p><p><b>
Preferred Qualifications:</b></p><ul><li>
Master's or PhD. in Computer Science, Computer Engineering</li></ul><ul><li>
10+ years of relevant experience</li><li>
10+ years of direct hands-on experience with C++ and Python</li><li>
10+ years of hands-on experience with Linux</li><li>
10+ years of direct hands-on experience with CAD SW development, Proven ability of software design principles, practices, and patterns</li><li>
Demonstratable knowledge of data structures, algorithms and design patterns</li><li>
Experience in the areas of RTL Synthesis (System Verilog -&gt; Netlist), Clock Tree Optimization, Exposure to VLSI design concepts, logic design</li><li>
Excellent interpersonal and analytical skills with the ability to work independently, and create customer-facing applications</li><li>
Experience with the following: Git, LSF, JIRA, GCC and other related technologies</li></ul><p></p><p><b>
Minimum Qualifications:</b></p><ul><li>Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.</li></ul>
OR<br>
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.<br>
OR<br>
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.<p></p><div><p>
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).</p></div><p></p><p><b>
To all Staffing and Recruiting Agencies</b>: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.</p><p><b>
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.</b></p><p></p><p>
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.</p><p></p><p><b><br>
Pay range </b><b>and Other Compensation &amp; Benefits</b><b>:
</b></p>$164,000.00 - $246,000.00<p></p><p>
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer &ndash; and you can review more details about our US benefits at this link.</p><p></p><p>
If you would like more information about this role, please contact Qualcomm Careers.</p></div>

EDA/CAD SW Engineer

Amazon.com

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><div>
As a Senior Design Verification Engineer, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms.<br>
<br>
You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:
<br>
<br>
<ul><li>Architect and implement verification environments for complex functional blocks
</li><li>Create and enhance verification environments using SystemVerilog and UVM
</li><li>Develop comprehensive test plans through collaboration with design engineers, SW and architects
</li><li>Implement coverage measures for stimulus and corner-case scenarios</li><li>Participate in test plan and coverage reviews</li><li>Drive complex RTL and TB debugs</li><li>Drive UPF based low power verification</li><li>Contribute to verification activities across simulation and emulation platforms</li><li>Work on creating the automation scripts to support DV methodologies</li><li>Create infrastructure to performs system level performance analysis<br>
</li></ul></div><h2 class="jobSectionHeader"><b>BASIC QUALIFICATIONS</b></h2><ul><li>Bachelor's degree in Electrical Engineering or a related field</li><li>Knowledge of hardware platforms</li><li>Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing</li><li>Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing</li><li>Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design</li><li>Experience with industry standard tools and scripting languages (Python or Perl) for automation</li><li>Experience in object-oriented design skills</li><li>10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks</li><li>Experience with RTL development environments</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Master's degree or Ph.D. degree in Electrical Engineering or related field</li><li>Experience with ARM and various DSP ISAs</li><li>Experience in system-level debugging</li><li>Experience with transaction level modeling</li><li>Knowledge of SoC architecture</li><li>Experience communicating technical details verbally and in writing</li><li>Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols</li><li>Experience with formal verification methods Experience with Low power verification methods</li><li>Experience with Baremetal processor environments</li><li>Familiarity with industry standard I/O interfaces</li><li>FPGA and emulation platform knowledge</li></ul><br>
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.</div>

Senior Design Verification Engineer, HW Compute Group

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
SOC/IP VERIFICATION ENGINEER</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD&rsquo;s graphics processor IP, resulting in no bugs in the final design.</div><div></div><div><b><br>
THE PERSON:</b></div><div>
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified</li><li>
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases</li><li>
Estimate the time required to write the new feature tests and any required changes to the test environment</li><li>
Build the directed and random verification tests</li><li>
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues</li><li>
Review functional and code coverage metrics &ndash; modify or add tests or constrain random tests to meet the coverage requirements</li></ul><div></div><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
Proficient in IP level ASIC verification</li><li>
Proficient in debugging firmware and RTL code using simulation tools</li></ul><ul><li>
Proficient in using UVM testbenches and working in Linux and Windows environments</li><li>
Experienced with Verilog, System Verilog, C, and C++</li><li>
Graphics pipeline knowledge</li><li>
Developing UVM based verification frameworks and testbenches, processes and flows</li><li>
Automating workflows in a distributed compute environment.</li></ul><ul><li>
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process</li><li>
Strong background in the C++ language, preferably on Linux with exposure to Windows platform</li><li>
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language</li><li>
Good working knowledge of SystemC and TLM with some related experience.</li><li>
Scripting language experience: Perl, Ruby, Makefile, shell preferred.</li></ul><ul><li>
Exposure to leadership or mentorship is an asset</li><li>
Desirable assets with prior exposure to video codec system or other multimedia solutions.</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul><p></p><p><br>
#LI-SG</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

SOC/IP VERIFICATION ENGINEER

Analog Devices

<div><div>Come join Analog Devices (ADI) &ndash; a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.</div><div></div><div>
ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.</div><div></div><div>
About Analog Devices</div><div>
Analog Devices, Inc. (NASDAQ: <div>ADI</div> ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible&trade;. Learn more at <div>www.analog.com</div> and on <div>LinkedIn</div> and <div>Twitter (X)</div>.</div><div></div><div><br>
Digital Design Engineer</div><div></div><div>
Main Responsibilities:</div><ul><li>
RTL Implementation of various SerDes design modules using SystemVerilog</li><li>
Unit level and top level testbench creations and verification</li><li>
Architecture development and design specifications</li><li>
Create and manage verification plans and regression tests</li><li>
Take part in all aspects of design success from conception to production</li><li>
Contribute to bench validation</li><li>
Work and collaborate effectively in a multi-cultural and multi-site environment</li></ul><div></div><div>
Preferred Qualifications:</div><ul><li>
BS or MS in Electronics Engineering with specialization in Digital IC Design</li><li>
Hand-on experience with ASIC and FPGA digital design, verification and product development methodologies</li><li>
Experience in high speed and low power RTL design and verification using Hardware Description Languages (preferably System Verilog)</li><li>
Experience with EDA tools form such as Synopsys, Cadence, Xilinx/AMD and Altera/Intel for ASIC and FPGA design</li><li>
Experience in synthesis, timing closure, linting, constrained and random verification, and logic equivalence checking</li><li>
Familiarity with UVM verification concepts</li><li>
Familiarity with digital signal processing and image processing concepts</li><li>
Strong analytical thinking and problem-solving skills</li><li>
Excellent written and verbal communication skills to work both independently and collaboratively as a part of a team</li><li>
Self-driven, motivated and passionate learner</li></ul><div></div><div><i>
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position &ndash; except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) &ndash; may have to go through an export licensing review process.</i></div><div></div><div><i>
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.</i></div><div></div>
Job Req Type: Graduate Job<br>
<div></div>
Required Travel: Yes, 10% of the time</div><div></div>

Engineer, Digital Design Engineering

NVIDIA

<div><p>We are now looking for a Senior ASIC Design Engineer - DFX</p><p></p><p>
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI &mdash; the next era of computing. NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life&rsquo;s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.</p><p></p><p><b>
What You&rsquo;ll Be Doing:</b></p><ul><li><p>
As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You&rsquo;ll help drive innovation across the full silicon lifecycle&mdash;from pre-silicon to post-silicon&mdash;while mentoring and collaborating with cross-functional teams.</p></li><li><p>
Own the architecture, design, and verification of DFT IPs for cutting-edge SoC designs.</p></li><li><p>
Develop, deploy, and enhance DFT methodologies for scalability and future product needs.</p></li><li><p>
Define and align feature sets by working closely with architects, platform, and software teams.</p></li><li><p>
Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.</p></li><li><p>
Create and execute test plans to support both functional and DFT full-chip verification.</p></li><li><p>
Support post-silicon bring-up and validation efforts including debug and issue resolution.</p></li><li><p>
Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.</p></li></ul><p></p><p><b>
What We need to see:</b></p><ul><li><p>
Master&rsquo;s degree (or equivalent experience) in Electrical Engineering or related field.</p></li><li><p>
5+ years of hands-on experience in SoC architecture, RTL design, and verification.</p></li><li><p>
Strong proficiency in micro-architecture and RTL development using Verilog.</p></li><li><p>
Experience with formal verification using JasperGold is a plus.</p></li><li><p>
Deep expertise in DFT design, methodology, and implementation.</p></li><li><p>
Familiarity with related domains such as clocking, STA, place &amp; route, and power optimization.</p></li><li><p>
Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.</p></li><li><p>
Proficiency in scripting languages such as Python, Perl, or Tcl.</p></li><li><p>
Excellent communication skills and a collaborative mindset&mdash;with a curiosity and passion for solving complex technical challenges.</p></li></ul><p></p><p>
This is your chance to join a high-impact team driving the foundation of next-generation semiconductor innovation. If you&rsquo;re passionate about DFT and SoC architecture, and want to work in a fast-paced, collaborative environment where your ideas make a difference&mdash;we&rsquo;d love to hear from you.</p><p></p>
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.<p></p><div><div><div><div><div><div><div><p>
You will also be eligible for equity and benefits.</p></div></div></div></div></div></div></div><p></p>
Applications for this job will be accepted at least until October 28, 2025.<p></p>
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.</div><p></p>

Senior ASIC Design Engineer - DFX

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<p>
As an AMD intern, you&rsquo;ll be placed at the epicenter of the AI ecosystem, working alongside experts and industry pioneers. You&rsquo;ll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide. Whether you&rsquo;re an undergrad or a PhD student, your contributions matter&mdash;and your experience here will be a launchpad for what comes next.</p><p></p><p><b><br>
JOB DETAILS:</b></p><ul><li><b>
Location:</b> San Jose, CA, USA</li><li><b>
Onsite: </b>This role requires the student to work full-time (40 hours a week) onsite from the San Jose office throughout the duration of the internship term.</li><li><b>
Duration:</b> May 18, 2026 - August 7, 2026 <b>or</b> June 22, 2026 &ndash; September 11, 2026</li></ul><p></p><p><b><br>
WHAT YOU WILL BE DOING:</b></p><p></p><p><br>
We are seeking a highly motivated Automotive Functional Safety Engineering Intern to join our team. In this role -</p><ul><li>
You will support requirements management and traceability for automotive safety compliance.</li><li>
We will involve you in reviewing Safety Concepts and contributing to the specification and development of reusable RTL components for the Functional Safety (FuSa) library.</li><li>
You will participate in safety analyses such as DFMEA, DFA, and FMEDA on designs incorporating cutting-edge technologies from leading IP providers.</li><li>
We will train you to review verification, fault injection, and validation efforts across block-level verification and validation teams.</li><li>
You will help prepare work products for ISO26262 and IEC61508 assessments.</li></ul><p></p><p><b><br>
WHO WE ARE LOOKING FOR:</b></p><ul><li>
You are currently enrolled in a US based University in Master&rsquo;s program majoring in Computer Engineering or Electrical Engineering or a related field.</li><li>
If you have knowledge and/or experience with any of the following technical skills (or related areas) &ndash;<ul><li>
Academic experience in designing or analyzing RTL blocks for an SOC, ASIC or FPGA</li><li>
Understanding of safety mechanisms such as Parity, ECC, CRC, Watchdog timer, Voltage/temperature monitoring</li><li>
Familiarity with SOC features such as Microprocessors, AXI Interconnect, DDR Controller and GPU</li><li>
Basic understanding of synthesis and place&amp;route processes in SOC/ASIC or FPGA design context</li><li>
Understanding of testbenches for verification of RTL designs</li><li>
Understanding of fault injection simulations and fault grading</li><li>
Simulation and debugging experience using VCS, IES, Verdi or similar</li><li>
Experience with silicon validation of processor based designs</li><li>
Experience in building automation using scripting languages as PERL, Python or TCL</li><li>
Fluent in working with Linux environment and version control systems such as Git or Perforce</li></ul></li></ul><div><b><i>
Note: </i></b><i>By submitting your application, you are indicating your interest in AMD intern positions. We are recruiting for multiple positions, and if your experience aligns with any of our intern opportunities, a recruiter will contact you.</i></div><div></div><div><i><br>
#LI-DNI</i></div>
Qualifications:
<div><i>
Benefits offered are described:</i><i> </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

Summer 2026 Masters Automotive Functional Safety Engineering Intern

<div><p>NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life&rsquo;s work , to amplify human creativity and intelligence. As an NVIDIAN, you&rsquo;ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!</p><p></p><p>
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.</p><p></p><p><b>
What you'll be doing:</b></p><ul><li><p>
As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression.</p></li><li><p>
Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.</p></li><li><p>
In addition, you will help develop and deploy DFT methodologies for our next generation products.</p></li><li><p>
Be apart of innovation to strive improve the quality of DFT methods.</p></li><li><p>
You will also need to work with multi-functional teams to incorporate DFT features into the chip.</p></li><li><p>
Occasional travel and also some late hours online meetings involved during critical milestones.</p></li></ul><p></p><p><b>
What we need to see:</b></p><ul><li><p>
BSEE or MSEE from reputed institutions or equivalent experience.</p></li><li><p>
2+ Years of experience preferably in Design for testability (DFT)</p></li><li><p>
You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.</p></li><li><p>
Experience in RTL and Gates verification and simulation.</p></li><li><p>
You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.</p></li><li><p>
Strong DFT knowledge in Scan ATPG, compression techniques and memory test.</p></li><li><p>
Strong analytical and problem solving skills.</p></li><li><p>
Expert coding skills in industry standard scripting languages.</p></li><li><p>
Extraordinary written and oral communication skills with the curiosity to work on rare challenges.</p></li></ul><p></p><p>
NVIDIA is widely considered to be one of the technology world&rsquo;s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer.</p><p></p><p>
#LI-Hybrid</p></div><p></p>

DFT Engineer

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