asic verification engineer

NVIDIA

<div><p>NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.</p><p></p><p>
NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life&rsquo;s work , to amplify human creativity and intelligence. As an NVIDIAN, you&rsquo;ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! In this position, you will be expected to plan and implement IP/Cluster/SOC functional verification of designs that constitute our Graphics Processors and Tegra SOCs. You would work on creating regression plans for code as well as functional coverage closure. You would perform pre-silicon validation activities such as XPROP simulations and GLS.</p><p></p><p><b>
What you&rsquo;ll be doing:</b></p><ul><li><p>
Own ASIC verification of IP/Cluster for complicated designs in RTL.</p></li><li><p>
Work with HW architects and designers to make the right implementation choices.</p></li><li><p>
Interact with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.</p></li><li><p>
You will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.</p></li><li><p>
Partner with and enable FPGA and S/W teams to ensure that S/W is tested.</p></li><li><p>
Be involved with post-silicon verification and debug.</p></li></ul><p></p><p><b>
What we need to see:
</b></p><ul><li><p>BS / MS or equivalent experience.</p></li><li><p>
2+ years of design experience.</p></li><li><p>
Experience in ASIC verification of complex design units for at least one or two projects.</p></li><li><p>
Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).</p></li><li><p>
Exposure to System Verilog and UVM based methodology for ASIC verification is highly desired.</p></li></ul><p></p><p><b>
Ways to stand out from the crowd:
</b></p><ul><li><p>Knowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.</p></li><li><p>
Good debugging and problem solving skills.</p></li><li><p>
Scripting knowledge (Python/Perl/shell).</p></li><li><p>
Good interpersonal skills and ability &amp; desire to work as a part of a team.</p></li></ul><p></p><p>
NVIDIA is widely considered to be one of the technology world&rsquo;s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.</p><p></p><p>
#LI-Hybrid</p></div><p></p>

ASIC Verification Engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
Verification Engineer</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
We are currently looking for Lead ASIC Verification Engineers who will be involved in all aspects of AMD's next generation Data center network products. This includes verifying designs using the latest UVM standard and developing comprehensive test plans to ensure coverage closure. The position allows exposure to all aspect of ASIC design stages.</div><div></div><div><br>
Our products are aimed at making Data Centre Networking solutions more effective. This is a highly strategic and important part of AMD&rsquo;s business, targeting a set of customers that includes the most successful internet and cloud companies in the world.</div><div></div><div><br>
Successful candidate will lead the verification effort and work alongside an experienced design and architecture teams and will thus have enormous opportunities for learning and self-development. The position is likely to require some travel.</div><div></div><div><b><br>
THE PERSON:</b></div><ul><li>
Creative innovator and thinker who loves technical problems and detail-oriented tasks</li><li>
Exhibits relentless commitment to help the team meet quality and development goals on schedule with high quality</li><li>
Drives to learn and perform at their highest potential in a technical capacity</li><li>
Thrives in both a team environment and in individual contribution.</li><li>
Able to lead a small team of engineers working towards a common objective</li><li>
Able to learn independenly and acquire new skills required for the job</li><li>
Communicates openly and clearly in meetings, presentations, emails, and reports</li></ul><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified</li><li>
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases</li><li>
Estimate the time required to write the new feature tests and any required changes to the test environment</li><li>
Build the directed and random verification tests</li><li>
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues</li><li>
Review functional and code coverage metrics &ndash; modify or add tests or constrain random tests to meet the coverage requirements</li></ul><div></div><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
Proficient in IP level ASIC verification</li><li>
Proficient in debugging firmware and RTL code using simulation tools</li></ul><ul><li>
Proficient in developing UVM/SV testbenches</li><li>
Experienced with Verilog, System Verilog, C, and C++</li><li>
Experience with PCIe and/or Ethernet protocols</li><li>
Automating workflows in a distributed compute environment.</li></ul><ul><li>
Exposure to simulation profile, efficiency improvement, acceleration</li><li>
Scripting language experience: Python, Ruby, Makefile, shell preferred.</li></ul><ul><li>
Exposure to leadership or mentorship is an asset</li><li>
Desirable assets with prior exposure to network processors.</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

Verification Engineer

CoMira Solutions PK

<p><b>CoMira Solutions is Hiring &ndash; Senior Verification/Design Engineer</b></p><p>We&rsquo;re looking for a <b>hands-on engineer</b> with expertise in <b>digital ASIC verification</b> using <b>SystemVerilog/UVM</b>.</p><p><b>Key Responsibilities:</b></p><ul><li>Develop and verify RTL design implementations</li><li>Build UVM environments, test benches &amp; verification components</li><li>Plan, implement &amp; analyze functional coverage</li><li>Debug verification environments &amp; recreate field issues</li><li>Work with protocols like <b>Ethernet (802.3), PCIe, CXL</b>, and security algorithms</li></ul><p><b>Requirements:</b></p><ul><li>3&ndash;5 years of relevant experience</li><li>Strong in <b>SystemVerilog, UVM, scripting (Perl/Python/Shell)</b></li><li>Familiar with <b>QuestaSim, VCS, or Cadence Incisive</b></li><li><b>Bachelors/Masters</b> in Electrical or Computer Engineering</li></ul><p><b>How to Apply:</b> Send your resume to <b>Huma.asif@comira.pk</b></p><p>Job Type: Full-time</p><p>Work Location: In person</p>

Design Verification Engineer

Credo Semiconductor

<div><p><b>Credo is engineering the future of high-speed connectivity for the AI-driven world.</b> With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers.</p><p></p><p><br>
Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure.</p><p></p><p><br>
At Credo, you&rsquo;ll be part of a team of world-class technologists and engineers that thrive on pushing the limits of what&rsquo;s possible for some of the world&rsquo;s most important companies. Our portfolio includes cutting edge solutions including our software, <b>optical DSPs, PCIe/CXL products, SerDes IP, and advanced Active Electrical Cables</b> (AECs) all designed for maximum performance, energy efficiency, and scalability.</p><p></p><p><br>
We foster a culture of <b>technical excellence, collaboration, and continuous learning</b>, where your ideas can shape the future of connectivity. From silicon architects to systems engineers, every role at Credo contributes to solving real-world problems at scale.</p>
<p><b>
Join us and help us architect the next generation of disruptive networking technologies &mdash; because at Credo, We Connect</b>.</p><p></p><p><b><br>
About the Role</b></p>
<p>
We&rsquo;re looking for a Senior Digital Design Engineer to lead front-end ASIC design efforts, including architecture, implementation, and verification of complex logic blocks. You&rsquo;ll collaborate across design, verification, and physical teams to ensure successful tape-outs, while contributing to microarchitecture specs, IP integration, and chip bring-up. This role combines technical depth with cross-functional teamwork to deliver high-performance digital solutions.</p><p></p><p><b><br>
Responsibilities</b></p>
<ul>
<li>Write microarchitecture and/or design specifications.</li>
<li>Architect/design, implement, and debug complex logic blocks.</li>
<li>Understand and integrate complex IPs from internal and external IP vendors.</li>
<li>Support all front-end integration activities like Lint, CDC, Synthesis, and ECO.</li>
<li>Develop functional tests/testbenches and run functional RTL and Gate-Level verification/simulations.</li>
<li>Work with other ASIC Design/Verification, DFT and Physical Design Engineers in achieving a successful tape out.</li>
<li>Collaborate with Software, Firmware, Applications, and Systems teams to ensure a high-quality product.</li>
<li>Bring-up, validate, and debug functional features in the chip.</li></ul><br>
<p></p>
<p><b>
Basic Qualifications</b></p>
<ul>
<li>BS or MS in Electrical Engineering, Computer Engineering, or related field with 5&ndash;10 years of experience in digital ASIC design</li>
<li>Strong understanding of digital logic design, including synchronous and asynchronous interfaces</li>
<li>Proficiency in Verilog/SystemVerilog RTL design</li>
<li>Experience developing testbenches and test cases for block-level and top-level verification</li>
<li>Familiarity with UVM methodology</li>
<li>Hands-on experience with gate-level simulations, chip bring-up, and validation</li>
<li>Knowledge of synthesis and static timing analysis</li>
<li>Proficiency in scripting languages such as Python, Tcl, Perl, or Shell</li>
<li>Strong planning and estimation skills</li>
<li>Effective communicator and collaborative team player</li></ul><br>
<p></p>
<p><i>
The base salary range for this position is $140,000 &ndash; $170,000 a year. The base salary ultimately offered is determined through a review of education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.</i></p><p></p><p><b><i><br>
Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.</i></b></p><p></p><p><b><i><br>
If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email people@credosemi.com.</i></b></p></div>

Senior Digital Design Engineer

Broadcom

<div><div>Please Note:</div><div>
1. If you are a first time user, please create your candidate login account before you apply for a job.</div><div>
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Job Description:</div><div></div><div>
The Network Switch Group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multi-chip solutions to market over the last decade. The group develops ASIC's for L2/L3 switch routing. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several Terabits/sec. These networking ASIC's support a large number of ports ranging from 10/100Mb/s to 800Gb/s speeds as well as various line interfaces and protocols. Some of the Industries most celebrated Switching solutions like Trident and Tomahawk line of products are designed and developed by our teams.</div><div></div><div>
As one of Fortune magazine&rsquo;s &ldquo;Most Admired Companies&rdquo;, Broadcom promotes an open work environment, embracing change, taking risks and doing the impossible every day. Outstanding initiative and aggressive execution is at the core of who and what we are, and we take pride in outdoing, outsmarting and outselling the competition. With our culture of innovation rewarding brainpower and risk taking with industry-leading company ownership/benefits and competitive salary, this unique environment creates enormous opportunity for you.</div><div></div><div>
Your responsibilities include: &middot;</div><div></div><div>
Emulation and Silicon Validation of complex System on Chip ASIC design.</div><div></div><ul><li>Define, develop and implement test plans and execute on the test plan</li></ul><div></div><ul><li>Develop system level tests using tcl, itcl, python, C/C++ languages to verify networking switch chips and systems.</li></ul><div></div><ul><li>Create reusable design blocks, libraries and verification components for emulation</li></ul><div></div><ul><li>Debug and resolve Pre / Post Silicon failures, Collaborate Cross-functionally with Architecture, uArch and Design teams</li></ul><div></div><ul><li>Enable and support Software/Firmware teams with Emulation setup</li></ul><div></div><ul><li>Synthesize complex system on chip designs and map into various hardware emulator platforms like Cadence Palladium or Mentor Veloce or Synopsys Zebu.</li></ul><div></div><div>
Additional Job Description :</div><div></div><ul><li>Total engineering experience required is typically a BS degree and 8+ years of experience, an MS degree and 6+ years of experience or a PhD and 3 years of experience or equivalent.</li></ul><div></div><ul><li>BS (EE/Electrical Engineering or CS/Computer Science) required, MS (EE or CS) preferred or equivalent.</li></ul><div></div><ul><li>Hands-on experience with Leadership qualities on driving ASIC / SoC verification flows and methodologies.</li></ul><div></div><ul><li>Good Knowledge in languages relevant to the ASIC verification process including Verilog, System Verilog, Tcl, iTcl, Perl, Python, Ruby, C/C++ and Unix Scripting.</li></ul><div></div><ul><li>Strong expertise in writing system level tests using C/C++, Tcl, iTcl, Perl and Python.</li></ul><div></div><ul><li>Excellent structured programming skills, data structures, algorithms,</li></ul><div></div><ul><li>Automation experience is a huge plus.</li></ul><div></div><ul><li>Strong Pre/Post Silicon debugging, analytical and independent problem solving ability.</li></ul><div></div><ul><li>Good knowledge in using industry standard debugging tools for both HW &amp; SW.</li></ul><div></div><ul><li>Must be a team player with good verbal and written communication skills.</li></ul><div></div><ul><li>Must be self-driven engineer with good project management and organizational skills to deliver high quality output in a timely manner</li></ul><div></div><div>
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.</div><div></div><div>
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.</div></div>

Emulation and Silicon Validation Engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
SOC Verification Design Engineer</b></div><div><br>
</div><div><b>THE ROLE:</b></div><div>
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD&rsquo;s graphics processor IP, resulting in no bugs in the final design.</div><div></div><div><b><br>
THE PERSON:</b></div><div>
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified</li><li>
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases</li><li>
Estimate the time required to write the new feature tests and any required changes to the test environment</li><li>
Build the directed and random verification tests</li><li>
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues</li><li>
Review functional and code coverage metrics &ndash; modify or add tests or constrain random tests to meet the coverage requirements</li></ul><div></div><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
Proficient in IP level ASIC verification with 7+years of experience</li><li>
Proficient in debugging firmware and RTL code using simulation tools</li></ul><ul><li>
Proficient in using UVM testbenches and working in Linux and Windows environments</li><li>
Experienced with Verilog, System Verilog, C, and C++</li><li>
Graphics pipeline knowledge</li><li>
Developing UVM based verification frameworks and testbenches, processes and flows</li><li>
Automating workflows in a distributed compute environment.</li></ul><ul><li>
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process</li><li>
Strong background in the C++ language, preferably on Linux with exposure to Windows platform</li><li>
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language</li><li>
Good working knowledge of SystemC and TLM with some related experience.</li><li>
Scripting language experience: Perl, Ruby, Makefile, shell preferred.</li></ul><ul><li>
Exposure to leadership or mentorship is an asset</li><li>
Desirable assets with prior exposure to video codec system or other multimedia solutions.</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul><p></p><p><br>
#LI-SG</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

SOC Verification Engineer

<div><div>Please Note:</div><div>
1. If you are a first time user, please create your candidate login account before you apply for a job.</div><div>
2. If you already have a Candidate Account, please Sign-In before you apply.</div><div></div><div>
Job Description:</div><div></div><div>
Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you will play a crucial part in ensuring the robustness and reliability of our HBM, DDR and SerDes designs through comprehensive Design for Test (DFT) verification strategies. You will work collaboratively with cross-functional teams to develop, implement, and validate DFT methodologies, guaranteeing that our products meet the highest quality standards.</div><div>
Key Responsibilities:</div><ul><li>
Implement and verify DFT methodologies specifically for HBM, DDR and SerDes designs.</li><li>
Collaborate with design and architecture teams to identify and define critical testability requirements.</li><li>
Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.</li><li>
Analyze DFT-related data and provide insights for continuous design improvements.</li><li>
Document verification processes, results, and best practices to enhance team knowledge and efficiency.</li><li>
Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.</li><li>
Working closely with STA and DI Engineers design closure for test</li><li>
Generating, Verifying &amp; Debugging Test vectors before tape release.</li><li>
Validating &amp; Debugging Test vectors on ATE during the silicon bring up phase</li><li>
Assisting with silicon failure analysis, diagnostics &amp; yield improvement efforts</li><li>
Interfacing with the customers, physical design and test engineering/manufacturing teams located globally</li><li>
Working closely with I/P DFT engineers &amp; other stakeholders</li><li>
Debugging customer returned parts on the ATE</li><li>
Innovating newer DFT solutions to solve testability problems in 3nm IPs &amp; beyond</li><li>
Automating DFT &amp; Test Vector Generation flows</li></ul><div></div><div>
 Skills/Experience:</div><ul><li>
Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)</li><li>
Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.</li><li>
Understanding of DFT methodologies, including scan, BIST, and ATPG.</li><li>
Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).</li><li>
Excellent analytical and problem-solving skills.</li><li>
Strong communication and teamwork abilities.</li><li>
The ability to work in a multi-disciplined, cross-department environment</li><li>
Solid knowledge in analog and digital circuit design, and device physics fundamentals</li><li>
Excellent problem solving, debug , root cause analysis and communication skills</li><li>
Experience working on ATE is a plus</li><li>
Familiarity with BIST logic for array and link testing is a plus</li><li>
Knowledge of AHB/APB/AXI buses is a plus</li></ul><div></div><div>
Education &amp; Experience:</div><ul><li>
Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience</li></ul><div></div><div>
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.</div><div></div><div>
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.</div></div>

STAFF IP DFT Verification Engineer

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