design verification engineer

CoMira Solutions PK

<p><b>CoMira Solutions is Hiring &ndash; Senior Verification/Design Engineer</b></p><p>We&rsquo;re looking for a <b>hands-on engineer</b> with expertise in <b>digital ASIC verification</b> using <b>SystemVerilog/UVM</b>.</p><p><b>Key Responsibilities:</b></p><ul><li>Develop and verify RTL design implementations</li><li>Build UVM environments, test benches &amp; verification components</li><li>Plan, implement &amp; analyze functional coverage</li><li>Debug verification environments &amp; recreate field issues</li><li>Work with protocols like <b>Ethernet (802.3), PCIe, CXL</b>, and security algorithms</li></ul><p><b>Requirements:</b></p><ul><li>3&ndash;5 years of relevant experience</li><li>Strong in <b>SystemVerilog, UVM, scripting (Perl/Python/Shell)</b></li><li>Familiar with <b>QuestaSim, VCS, or Cadence Incisive</b></li><li><b>Bachelors/Masters</b> in Electrical or Computer Engineering</li></ul><p><b>How to Apply:</b> Send your resume to <b>Huma.asif@comira.pk</b></p><p>Job Type: Full-time</p><p>Work Location: In person</p>

Design Verification Engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
MTS SILICON DESIGN ENGINEER</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
As an MTS Design Verification Engineer in AMD&rsquo;s Infinity (Data) Fabric team, you will be a technical engineer responsible for driving verification of high-performance, scalable fabric IP that connects compute, memory, and I/O subsystems across AMD&rsquo;s CPUs, GPUs, and APUs.</div><div></div><div><b><br>
THE PERSON:</b></div><div>
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.</div><div></div><div><b><br>
KEY RESPONSIBLITIES:</b></div><ul><li>
Own verification execution for complex Data Fabric IP blocks and subsystems from spec review through tape-out.</li><li>
Lead test plan creation and sign-off, integrating both constrained-random and directed testing methodologies.</li><li>
Drive coverage-driven verification &mdash; define, track, and close both functional and code coverage goals.</li><li>
Collaborate cross-functionally with design, architecture, and performance teams to debug complex issues and ensure first-pass silicon success.</li><li>
Mentor and guide junior and mid-level verification engineers, reviewing their code, test plans, and coverage results</li><li>
Identify and drive verification methodology improvements, automation, and process optimizations to enhance team productivity.</li><li>
Participate in post-silicon debug and validation, assisting in recreating and root-causing issues found in lab or customer systems</li></ul><div></div><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
Expertise in System Verilog &amp; UVM for block- and system-level verification of complex IP.</li><li>
Proven track record of leading verification on large, high-performance ASICs or SoCs from concept to tape-out.</li><li>
Strong knowledge of computer architecture and interconnect/fabric protocols.</li><li>
Proficiency in EDA tools such as Synopsys VCS</li><li>
Advanced debug skills for simulation and waveform analysis.</li><li>
Scripting proficiency in Python, Perl, or similar for automation and flow development.</li><li>
Experience with coverage closure strategies, regression management, and verification metrics reporting.</li><li>
Familiarity with formal verification concepts and tools is a plus.</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul><p><br>
#LI-BM2
</p>Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

Tata Consultancy Services (TCS)

<div></div><div><div><div><div><p>Job Role: VLSI Design Verification Engineer</p>
<p>Required Skill: SystemVerilog, VLSI DV</p>
<p>Experience: 4-7 years<br>
Location: Hyderabad/ Bangalore<br>
Must Have Skill:
</p><ul><li>3+ years Design Verification experience in SystemVerilog / C++</li>
<li>Experience in test planning and debugging complex designs</li>
<li>Full silicon design lifecycle experience</li>
<li>Strong background in developing UVM Testbenches from scratch</li>
<li>Deep understanding of Computer Architecture</li></ul><br>
<div>
</div><p>Good To Have: Experience with caches and memory subsystems
</p><p>Roles &amp; Responsibility : Job requires experience in VLSI DV skills.</p>
</div></div></div><div><div><div><b>Location</b></div>
<div>Hyderabad</div>
</div><div><div><b>Job Function</b></div>
<div>TECHNOLOGY</div>
</div><div><div><b>Role</b></div>
<div>Engineer</div>
</div><div><div><b>Job Id</b></div>
<div>374256</div>
</div><div><div><b>Desired Skills</b></div>
<div>VLSI</div>
</div></div><p>Desired Candidate Profile
</p><div><div><b>Qualifications</b> : BACHELOR OF ENGINEERING</div></div></div><div></div>

VLSI Design Verification Engineer

Analog Devices

<div><div>Come join Analog Devices (ADI) &ndash; a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.</div><div></div><div>
ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.</div><div></div><div>
About Analog Devices</div><div>
Analog Devices, Inc. (NASDAQ: <div>ADI</div> ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible&trade;. Learn more at <div>www.analog.com</div> and on <div>LinkedIn</div> and <div>Twitter (X)</div>.</div><div></div><div><div><div><br>
Verification Engineer</div></div><div></div><div><div><br>
The ATE Group is currently seeking a motivated Verification Engineer for the IC development of new products. Products in this strategy are comprised of integrated high speed and precision signal chains targeted towards Automated Test Equipment (ATE) applications. Product designs utilize both advanced internal BiCMOS SiGe processes as well as standard 0.18um CMOS processes and fine line CMOS processes. These designs are then combined on a laminate package to provide a custom SIP (System In a Package) solution otherwise known as a chiplet.</div></div><div><div>
The candidate&rsquo;s responsibilities will include system level verification of the products including simulation of digital and mixed signal circuits including high speed drivers and receivers, DACs, SPI interfaces, calibration routines and digital controls. This is a multi-die verification effort utilizing both Verilog and spice simulators. A Verification plan will be created at the product start determining the verification methods to be utilized and the block model plans. Duties also include working with evaluation engineers to compare and contrast simulation and lab results. The ideal candidate is a self-motivated individual and fast learner with strong technical, analytical and communication skills. The candidate will have the opportunity to learn system level design experience, work with newly developed internal BiCMOS processes and collaborate closely with an experienced development team.</div></div><div><div>
Job responsibilities will include, but are not limited to, the following:</div></div><div><ul><li><div>
Develop test bench environments and directed functional, random, and constrained random tests. Implement coverage driven verification methodologies. Create functional coverage metrics. Ensure these environments allow verification, design, product, and test engineers to efficiently develop functional test cases.</div></li></ul></div><div><ul><li><div>
Define and develop block level modeling and verification strategies based on design requirements and architecture</div></li></ul></div><div><ul><li><div>
Specify, and perform as necessary, block and chip level RTL, gate, and mixed signal co-simulation regressions. Track progress against verification plan</div></li></ul></div><div><ul><li><div>
Work with designers and product/apps engineers to achieve functional coverage goals and to debug the design and environment</div></li></ul></div><div><ul><li><div>
Participate in project meetings</div></li></ul></div><div><div>
Qualifications:</div></div><div><ul><li><div>
Minimum requirement of BSEE</div></li></ul></div><div><ul><li><div>
Knowledge of Analog circuits and CAD tools (Cadence Virtuoso).</div></li></ul></div><div><ul><li><div>
Ability to problem solve at the circuit and system level</div></li></ul></div><div><ul><li><div>
Good presentation and writing/communication skills.</div></li></ul></div></div><div><div><ul><li><div>
Ability to collaborate in a team environment and across organizations</div></li></ul></div></div><div></div><div><i>
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position &ndash; except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) &ndash; may have to go through an export licensing review process.</i></div><div></div><div><i>
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.</i></div><div></div>
Job Req Type: Graduate Job<br>
<div></div>
Required Travel: Yes, 10% of the time</div><div></div>

Engineer, Design Verification Engineer

Meta

<div>Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of an agile team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook&rsquo;s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.<br>
<br>
<br>
<h3 class="jobSectionHeader"><b>ASIC Engineer, Performance &amp; Package Verification Responsibilities:
</b><br>
</h3><ul><li>Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification</li><li>
Develop functional tests based on verification test plan</li><li>
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage</li><li>
Debug, root-cause and resolve functional failures in the design, partnering with the Design team</li><li>
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality</li><li>
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry</li></ul><br>
<br>
<br>
<h3 class="jobSectionHeader"><b>Minimum Qualifications:</b><br>
</h3><ul><li>
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience</li><li>
Track record of 'first-pass success' in ASIC development cycles</li><li>
8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification</li><li>
8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies</li><li>
Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation</li><li>
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments</li><li>
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle</li></ul><br>
<br>
<br>
<h3 class="jobSectionHeader"><b>Preferred Qualifications:</b><br>
</h3><ul><li>
2+ years of experience in performance verification for CPU, GPU, or AI accelerator architectures</li><li>
Hands-on experience with architecture-level performance test planning, execution, and closure</li><li>
Experience with compute and/or memory subsystem and/or collective performance verification</li><li>
Familiarity with host and system-level concepts for performance verification</li><li>
Experience with chiplet-based architectures and package-level integration verification</li><li>
Exposure to industry-standard performance benchmarks and workload characterization</li><li>
Prior experience with fullchip or package-level integration projects</li></ul><br>
<br>
<br>
<h3 class="jobSectionHeader"><b>About Meta:</b><br>
</h3>
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today&mdash;beyond the constraints of screens, the limits of distance, and even the rules of physics.<br>
<br>
<br>
<div>Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
<br>
<br>
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.<br>
<br>
$173,000/year to $249,000/year + bonus + equity + benefits<br>
<br>
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.</div></div>

ASIC Engineer, Performance & Package Verification

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
SOC Verification Design Engineer</b></div><div><br>
</div><div><b>THE ROLE:</b></div><div>
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD&rsquo;s graphics processor IP, resulting in no bugs in the final design.</div><div></div><div><b><br>
THE PERSON:</b></div><div>
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified</li><li>
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases</li><li>
Estimate the time required to write the new feature tests and any required changes to the test environment</li><li>
Build the directed and random verification tests</li><li>
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues</li><li>
Review functional and code coverage metrics &ndash; modify or add tests or constrain random tests to meet the coverage requirements</li></ul><div></div><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
Proficient in IP level ASIC verification with 7+years of experience</li><li>
Proficient in debugging firmware and RTL code using simulation tools</li></ul><ul><li>
Proficient in using UVM testbenches and working in Linux and Windows environments</li><li>
Experienced with Verilog, System Verilog, C, and C++</li><li>
Graphics pipeline knowledge</li><li>
Developing UVM based verification frameworks and testbenches, processes and flows</li><li>
Automating workflows in a distributed compute environment.</li></ul><ul><li>
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process</li><li>
Strong background in the C++ language, preferably on Linux with exposure to Windows platform</li><li>
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language</li><li>
Good working knowledge of SystemC and TLM with some related experience.</li><li>
Scripting language experience: Perl, Ruby, Makefile, shell preferred.</li></ul><ul><li>
Exposure to leadership or mentorship is an asset</li><li>
Desirable assets with prior exposure to video codec system or other multimedia solutions.</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul><p></p><p><br>
#LI-SG</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

SOC Verification Engineer

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