digital design engineer

NVIDIA

<div><div>We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI &mdash; the next era of computing. NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life&rsquo;s work, to amplify human imagination and intelligence. Make the choice to join our diverse team today!</div><div></div><div>
As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify the design and implementation of our cutting edge SerDes IPs. This ground breaking technology will enable and accelerate gaming, artificial intelligence, deep learning, and autonomous driving. We have put together a best-in-class team that delivers IPs that will be consumed by standard as well as industry-leading proprietary high-speed protocols!</div><div></div><div>
What you&rsquo;ll be doing:</div><ul><li><div>
Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.</div></li><li><div>
Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.</div></li><li><div>
Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.</div></li><li><div>
Write and implement test plan and thoroughly verify a design in a product shipment focused / compressed schedule.</div></li><li><div>
Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.</div></li></ul><div></div><div>
What we need to see:</div><ul><li><div>
Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering</div></li><li><div>
At least 5 years of validated experience.</div></li><li><div>
Background in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog a must.</div></li><li><div>
Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.</div></li><li><div>
Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.</div></li></ul><div></div><div>
Ways to stand out from the crowd:</div><ul><li><div>
Expertise in bus or interconnect protocols (e.g. PCI Express, USB, SATA) a huge plus.</div></li><li><div>
Experience in verifying complex SerDes system, understanding mixed-signal designs, and have experience in modeling of analog circuits a huge plus.</div></li><li><div>
Perl, Python, C/C++ programming language experience.</div></li><li><div>
Good debugging and analytical skills.</div></li><li><div>
Good interpersonal skills &amp; dream to work as a phenomenal teammate.</div></li></ul><div></div>
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.<div></div><div><div><div><div><div><div><div><div>
You will also be eligible for equity and <div>benefits</div>.</div></div></div></div></div></div></div></div><div></div>
Applications for this job will be accepted at least until February 27, 2026.<div></div><div>
This posting is for an existing vacancy.</div><div>
NVIDIA uses AI tools in its recruiting processes.</div><div></div>
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.</div><div></div>

Senior Digital Design Verification Engineer - Hardware

Larsen & Toubro

<div>
 <strong>
  Roles
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Digital Design Engineer for analog mixed signal IP/IC.
  </li>
  <li>
   Direct responsible individual for architecting the optimized digital solution for complex mixed signal IP/IC.
  </li>
  <li>
   Responsibilities:
  </li>
  <ul>
   <li>
    End to end responsible for architecture, feasibility and modelling of analog mixed solutions through digital designs techniques.
   </li>
   <li>
    Create digital IP wrapper for analog design ensuring seamless integration at the SOC level.
   </li>
   <li>
    Work out the DFT solutions needed to detect manufacturing defects.
   </li>
   <li>
    Understanding the customer requirements, bench marking and doing cost analysis through die size estimation, power consumption, test time.
   </li>
   <li>
    For meeting the quality, timelines and milestones for successful and flawless execution of projects.
   </li>
   <li>
    Contribute to setting the flow and methodology, quality Matrix for RTL sign-off analog in mixed signal design.
   </li>
   <li>
    Represent the organization in various industry forums, academic circles, conferences and workshops to show case innovative solutions.
   </li>
   <li>
    Working with cross functional teams during development cycle and then with PE/TE team post tape out.
   </li>
   <li>
    Drive culture of innovation to ensure the IP/IC we are doing are best in class benchmarking with competition.
   </li>
   <li>
    Guiding and mentoring the young engineers to develop skills and to acquire critical design competencies.
   </li>
  </ul>
 </ul>
</div>


RTL Designer

Micron Technology

<div><p><b>Our vision is to transform how the world uses information to enrich life for </b><b><i>all </i></b><b>.
</b></p><p>Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
</p><p></p><div><p>As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. We are engaged in developing groundbreaking silicon-to-systems solutions &ndash; right from technology development and advanced memory designs to product development, systems design and validation resulting in premier memory solutions.
<br>
In this position, you will collaborate with Micron&rsquo;s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.
</p></div><p></p><div><div><div><div><div><div><div><div><div><p>The Senior Design Engineer is responsible for designing, simulating, and optimizing DRAM circuits while supporting the development of digital and analog circuitry used in advanced memory products. This role collaborates globally across design, verification, product engineering, test, probe, process integration, assembly, and marketing to ensure manufacturable, high‑quality, cost‑optimized solutions. The position drives innovation in future memory generations and supplies to silicon‑to‑system development in a dynamic engineering environment.
</p><p></p><p><b>Responsibilities
</b></p><ul><li><p>Design digital, analog, and memory core circuits using CMOS logic and transistors, implementing device specifications from concept to solution.
</p></li><li><p>Create optimized floorplans for circuit placement, routing, power delivery, sense margins, array timing, and die size, including layout leadership.
</p></li><li><p>Conduct circuit simulations using FINESIM, HSPICE, and VERILOG; analyze power, performance, reliability, and parasitic impacts.
</p></li><li><p>Validate builds through reticle experiments, tape‑out revisions, and simulation‑to‑silicon correlation, identifying required schematic edits.
</p></li><li><p>Prepare and maintain design documentation while giving to best‑known practices and departmental training.
</p></li><li><p>Collaborate with global build, verification, product engineering, test, probe, process integration, assembly, and marketing teams to ensure manufacturability and quality.
</p></li><li><p>Lead layout and develop resources, track project tasks, and serve as the point of contact for design, layout, verification, and test issues.
</p></li><li><p>Prepare project status reports and lead design reviews to communicate progress and technical decisions.
</p></li></ul><p></p><p><b>Minimum Qualifications
</b></p><ul><li><p>Coursework in CMOS Circuit Design, VLSI, and Analog Circuit Design, with understanding of device reliability and circuit floor planning.
</p></li><li><p>Proficiency with Cadence Virtuoso, and experience simulating with FINESIM, HSPICE, and VERILOG.
</p></li><li><p>Strong analytical and problem‑solving skills with validated significant technical contributions and a record of innovation.
</p></li><li><p>Expertise in DRAM subsystem architecture, specification, operation, or design, including cross‑department technical leadership experience.
</p></li><li><p>Ability to proactively collaborate across multiple engineering organizations to optimize manufacturing quality, cost, reliability, and time‑to‑market.
</p></li></ul><p><b>Preferred Qualifications
</b></p><ul><li><p>Self‑motivated with strong problem‑solving abilities and an aim to discover new solutions.
</p></li><li><p>Deep knowledge of industry‑specific technologies and competitive trends.
</p></li><li><p>Excellent communication and interpersonal skills for multi-functional collaboration.
</p></li><li><p>BS or MS in Electrical Engineering or related field plus 6 years of experience in DRAM design, product, or system.
</p></li></ul></div></div></div></div></div></div></div></div></div><p></p><p>As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .
</p><p></p><p>Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.</p><p></p><p><b><br>
</b></p><p></p><p>To learn more about Micron, please visit <b>micron.com/careers
</b></p><p></p><p>For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron&rsquo;s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
</p><p></p><p>Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
</p><p></p><p>Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
</p><p></p><p>AI alert <b>: </b>Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
</p><p></p><p>Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.</p></div><p></p>

Senior Memory Design Engineer, HBM

CoreEl Technologies

<div><div><p>Role Overview:
</p><p>The Senior FPGA Design Engineer is responsible for architecting, designing, verifying, and integrating FPGA-based subsystems that form the backbone of advanced wireless communication and signal processing platforms. The role requires hands-on technical expertise in RTL development, FPGA tool flows, and hardware validation, along with the ability to work collaboratively with system, hardware, and firmware teams.</p><br>
<p></p>
<p>
Key Responsibilities</p>
<div>
<ul><li>FPGA Design &amp; Development</li></ul>
</div><ul><li>Translate system-level specifications and algorithmic models into synthesizable RTL architectures.</li>
<li>Develop RTL modules in VHDL/Verilog for control logic, DSP blocks, and high-speed interfaces.</li>
<li>Implement digital signal processing functions such as filtering, modulation/demodulation, channel coding/decoding (LDPC, Turbo, BCH, etc.).</li>
<li>Create timing and I/O constraints for synthesis, place-and-route, and static timing analysis.</li>
<li>Optimize design for timing, resource utilization, and power efficiency.</li>
<li>Generate FPGA bitstreams and support board-level validation.</li>
</ul><div><ul><li>Verification &amp; Validation</li></ul>
</div><ul><li>Develop self-checking test benches and functional verification environments.</li>
<li>Perform module-level and top-level simulations using ModelSim or XSIM.</li>
<li>Debug simulation mismatches and post-synthesis timing violations.</li>
<li>Support system integration and real-time testing on FPGA evaluation or custom boards (e.g., Zynq SoC, Artix/Kintex UltraScale).</li>
</ul><div><ul><li>Process &amp; Documentation</li></ul>
</div><ul><li>Follow internal FPGA design workflows which are aligned with ISO standards</li>
<li>Maintain design documents: FPGA architecture, Design document, interface specifications, verification reports, timing summaries, and utilization logs.</li>
<li>Participate in formal design reviews &mdash; Input Review, Output Review, V&amp;V Review, and Change Review &mdash; with review records maintained in MoMs.</li>
<li>Ensure all design baselines are version-controlled using SVN or equivalent tools.</li>
</ul><div><ul><li>Cross-Functional Collaboration</li></ul>
</div><ul><li>Work closely with system engineers to interpret waveform and communication specifications into hardware-friendly requirements.</li>
<li>Coordinate with hardware and firmware teams for FPGA-board integration and software interaction.</li>
<li>Support test engineers during on-board bring-up and system-level validation.</li>
</ul><div><ul><li>Mentoring &amp; Knowledge Sharing</li></ul>
</div><ul><li>Guide junior engineers in coding practices, simulation, and debugging techniques.</li>
<li>Contribute to internal FPGA knowledge base and reusable IP library development.</li>
</ul>
<p>Professional Skills:</p>
<ul>
<li>Strong RTL design skills using VHDL/Verilog</li>
<li>Thorough understanding of Xilinx FPGA&rsquo;s</li>
<li>Simulation and verification using ModelSim/XSIM</li>
<li>Hands-on experience with Xilinx Vivado, Intel Quartus, or equivalent FPGA toolchains.</li>
<li>Hands on with Zynq SoC or Zynq UltraScale+ platforms preferred</li>
<li>Hands-on synthesis, place &amp; route, static timing analysis, and constraint management.</li>
<li>Hands-on with AXI, DDR, Ethernet, UART, SPI, I2C, and other digital interfaces.</li>
<li>Experience with Zynq SoCs (PS-PL integration) or FPGA-based signal processing systems.</li>
<li>Familiarity with scripting (Tcl/Python/Shell) for simulation &amp; compilation automation</li>
<li>Configuration/Version control tools like SVN</li>
</ul>
<p>Desired Attributes/ Softskills</p>
<ul>
<li>Strong analytical and debugging ability at simulation and on-board levels which leads to decision making.</li>
<li>Attention to design quality, reusability, and adherence to coding guidelines.</li>
<li>Commitment to documentation and process discipline.</li>
<li>Ability to take ownership of module-level or subsystem-level FPGA delivery.</li>
<li>Collaborative team player with a continuous improvement mindset.</li></ul></div></div>

Senior FPGA Design Engineer

Analog Devices

<div><div>About Analog Devices</div><div>
Analog Devices, Inc. (NASDAQ: <div>ADI</div> ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible&trade;. Learn more at <div>www.analog.com</div> and on <div>LinkedIn</div> and <div>Twitter (X)</div>.</div><div></div><div><br>
Principal Mixed Signal Design Engineer<br>
<br>
About the Role<br>
As a Principal Mixed Signal Design Engineer, you will serve as a technical authority in the design and development of sophisticated mixed-signal integrated circuits. You will drive architecture decisions and technology roadmaps while leading complex projects from concept to production.<br>
Your deep expertise will enable you to make critical technical tradeoffs across analog and digital domains, devise innovative solutions to complex problems, and provide technical leadership that influences ADI's technology direction and methodology. You will be responsible for driving advancements in mixed-signal design while mentoring other engineers and representing ADI's technical excellence internally and externally.<br>
<br>
Key Responsibilities</div><ul><li>
Define and drive the architecture for complex mixed-signal ICs, making critical design decisions that balance performance, power, area, and time-to-market considerations</li><li>
Drive innovation in mixed-signal design approaches, developing new theories and methods that advance the company's technological capabilities</li><li>
Lead complex mixed-signal projects with significant business impact, directing work of engineering teams without formal management responsibility</li><li>
Oversee the integration of analog and digital IP, ensuring robust performance across varied operating conditions and process variations</li><li>
Provide authoritative technical expertise to resolve complex design challenges across multiple projects</li><li>
Partner with business leaders to influence product roadmaps and technology direction</li><li>
Lead collaborative efforts across engineering disciplines, influencing decisions without direct authority</li><li>
Mentor engineering staff and build technical expertise within the organization</li></ul><div><br>
Must Have Skills</div><ul><li>
Strategic Architecture: Develop and implement architectural strategies for complex mixed-signal systems, making critical decisions that optimize performance, power, area, and manufacturability tradeoffs</li><li>
System-Level Integration: Apply expert-level understanding of system architecture to guide the integration of disparate analog and digital IP blocks</li><li>
Advanced Methodologies: Pioneer and establish best practices for mixed-signal design methodologies that address next-generation challenges</li><li>
Mixed-Signal IC Design: Apply expert-level knowledge to architect sophisticated mixed-signal circuits including power management ICs, ADCs, DACs, and PLLs</li><li>
Performance Optimization: Develop advanced techniques for optimizing circuits across multiple parameters including noise, timing, and power consumption</li><li>
Advanced CMOS Technology: Leverage deep understanding of CMOS processes and device physics to maximize circuit performance and yield</li><li>
Simulation &amp; Modeling: Apply sophisticated simulation techniques and develop advanced models to predict and optimize circuit performance under various conditions</li><li>
Layout &amp; Implementation: Guide physical design teams on implementation strategies to meet stringent performance requirements</li><li>
Verification Strategy: Devise comprehensive verification approaches to ensure robust functionality across all operating conditions</li><li>
Innovation Leadership: Drive technical innovation that results in patentable ideas and industry recognition</li><li>
Cross-functional Influence: Lead and influence technical approaches across organizational boundaries</li><li>
Problem Resolution: Resolve complex technical issues that span multiple domains, applying creative solutions to unprecedented challenges</li></ul><div><br>
Preferred Education and Experience</div><ul><li>
Master's degree in Electrical Engineering or related field with 10-15 years of relevant industry experience</li><li>
PhD with 8+ years of experience</li><li>
Proven track record of successfully leading complex mixed-signal projects from concept through production release</li></ul><div><br>
Why You&rsquo;ll Love Working at ADI<br>
At Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.<br>
Your expertise will shape the future of technology, and you&rsquo;ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.</div><div></div><div><i>
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position &ndash; except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) &ndash; may have to go through an export licensing review process.</i></div><div></div><div><i>
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.</i></div><div></div><div><i>
EEO is the Law: </i><div><i>Notice of Applicant Rights Under the Law</i></div><i>.</i></div>
Job Req Type: Experienced<br>
<div></div>
Required Travel: No<br>
<div></div>
Shift Type: 1st Shift/Days<div></div>
The expected wage range for a new hire into this position is $157,080 to $227,460.<ul><li><div>
Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.</div></li><li><div>
This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.</div></li><li><div>
This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.</div></li></ul></div><div></div>

Principal Engineer, Mixed Signal Designer

Synopsys

<div><h3 class="jobSectionHeader"><b>Alternate Job Titles:</b><ul><li>
Senior RTL Design Engineer</li><li>
IP RTL Engineer &ndash; PVT Sensors</li><li>
ASIC Design Engineer &ndash; RTL &amp; Microarchitecture</li><li>
SoC RTL Integration Specialist</li></ul></h3><h3 class="jobSectionHeader"><b>
We Are:</b></h3><p>
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p><h3 class="jobSectionHeader"><b>
You Are:</b></h3><p>
You are a passionate and driven RTL Design Engineer who thrives on translating complex specifications into robust, reusable, and high-performance digital hardware. With a strong foundation in microarchitecture and hands-on expertise in Verilog, you are excited to own and deliver IP subsystems from concept to silicon. You are motivated by challenges, eager to learn, and enjoy collaborating across diverse engineering teams. Your attention to detail ensures rigorous static checks and quality sign-offs, while your forward-thinking mindset drives continuous improvement in design flows and methodologies. You take pride in mentoring junior engineers and are committed to upholding the highest standards in RTL quality and integration.</p><p>
You bring a collaborative spirit, strong communication skills, and the confidence to tackle new technologies and design paradigms. You seek an environment where your expertise in IP-level RTL, clock domains, and SoC integration is valued, and where you can make a real impact on cutting-edge silicon products. If you are ready to shape the next generation of PVT sensing and telemetry subsystems, we invite you to be part of our inclusive and innovative team.</p><h3 class="jobSectionHeader"><b>
What You&rsquo;ll Be Doing:</b></h3><ul><li>
Own and develop IP-level microarchitecture and synthesizable RTL (Verilog) for advanced on-chip PVT (Process, Voltage, Temperature) sensing and telemetry subsystems.</li><li>
Define detailed microarchitecture/specifications and implement reusable, high-quality RTL that meets functional and performance goals.</li><li>
Perform rigorous static checks (lint, CDC) using industry-standard tools, ensuring disciplined waiver management and clean sign-offs.</li><li>
Drive synthesis, SDC constraint development, and timing analysis (QoR), collaborating closely with DV, PD, and DFT teams for integration and sign-off.</li><li>
Ensure Logic Equivalence Check (LEC) pass and seamless handoff to downstream teams, supporting comprehensive verification and physical design flows.</li><li>
Continuously improve RTL design flows and scripting, and mentor junior engineers on best practices in RTL quality, sign-off criteria, and design methodologies.</li><li>
Contribute to SoC-level integration, collaborating with cross-functional teams to achieve timing closure, coverage, and robust system performance.</li></ul><h3 class="jobSectionHeader"><b>
The Impact You Will Have:</b></h3><ul><li>
Deliver high-quality, robust RTL IP blocks that form the backbone of Synopsys&rsquo; leading-edge silicon solutions.</li><li>
Enhance the reliability and accuracy of on-chip PVT monitoring, enabling customers to achieve optimized performance and power efficiency.</li><li>
Drive continuous improvement in RTL design quality, verification coverage, and integration efficiency.</li><li>
Accelerate product development cycles through effective collaboration and proactive issue resolution.</li><li>
Mentor and uplift the technical capabilities of junior engineers, strengthening the overall team expertise.</li><li>
Contribute to Synopsys&rsquo; reputation as an innovation leader in semiconductor IP, helping customers succeed in highly competitive markets.</li></ul><h3 class="jobSectionHeader"><b>
What You&rsquo;ll Need:</b></h3><ul><li>
2&ndash;5 years hands-on experience in RTL design, microarchitecture, and IP integration using Verilog.</li><li>
Expertise in static checks: Lint and CDC analysis with tools such as SpyGlass, Questa, or Real Intent.</li><li>
Proficiency in synthesis and static timing analysis (STA) using DC/Genus and PrimeTime/Tempus; LEC sign-off using Formality/Conformal.</li><li>
Solid understanding of clock/reset architectures, clock domain crossing, FIFOs, and handshake mechanisms.</li><li>
Experience with AMBA protocols (AXI, AHB, APB) and SoC-level integration flows.</li><li>
Bonus: Exposure to low-power design methodologies (UPF/CPF), basics of DFT (scan/MBIST), and scripting with Python/TCL.</li><li>
Bonus: Experience with FPGA prototyping and validation.</li></ul><h3 class="jobSectionHeader"><b>
Who You Are:</b></h3><ul><li>
Analytical thinker with strong problem-solving skills and meticulous attention to detail.</li><li>
Effective communicator, able to collaborate with cross-functional teams and explain complex concepts clearly.</li><li>
Self-motivated and proactive, eager to take ownership and deliver results in a fast-paced environment.</li><li>
Adaptable and open to learning new tools, flows, and technologies.</li><li>
Team player who enjoys mentoring and supporting the professional growth of others.</li></ul><h3 class="jobSectionHeader"><b>
The Team You&rsquo;ll Be A Part Of:</b></h3><p>
You will join a dynamic and inclusive team of digital design experts focused on developing high-performance, reliable IP for on-chip sensing and telemetry. Our team values innovation, collaboration, and continuous learning. We work closely with verification, physical design, and DFT specialists to deliver best-in-class silicon IP that powers Synopsys&rsquo; industry-leading solutions. Together, we tackle complex design challenges and celebrate our successes as a unified group.</p><h3 class="jobSectionHeader"><b>
Rewards and Benefits:</b></h3><p>
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p></div>

Sr RTL Design Engineer

Cisco

Meet the Team
<br><br>
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With 2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
<br><br>
Your Impact
<br><br>
<ul>
<li>Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.</li>
<li>Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.</li>
<li>Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.</li>
<li>The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.</li>
</ul>
You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of technologies.
<br><br>
<b>Minimum Qualifications:</b><br>
<ul>
<li>Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 4-6 years of experience.</li>
<li>Knowledge of the latest innovative trends in DFT, test and silicon engineering.</li>
<li>Experience with Jtag protocols, Scan insertion and ATPG.</li>
<li>Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.</li>
<li>Knowledge of the latest innovative trends in DFT, test and silicon engineering.</li>
<li>Experience working with Gate level simulation, debugging with VCS and other simulators.</li>
<li>Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687</li>
<li>Strong verbal skills and ability to thrive in a multifaceted environment</li>
<li>Scripting skills: Tcl, Python/Perl.</li>
</ul>
<b>Preferred Qualifications:</b><br>
<ul>
<li>Test Static Timing Analysis</li>
<li>Post silicon validation using DFT patterns.</li>
</ul>
Why Cisco?
<br><br>
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
<br>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
<br>We are Cisco, and our power starts with you.

ASIC DFT Engineer

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