hardware verification engineer

Wipro

<div>Job Description<p></p><div><div><ul><li><div><b><br>
</b><br>
</div></li></ul></div></div><div><div><div><div>Job Title: Design Verification Engineer (Data Fabric Verification Engineer)
</div></div></div></div><div><div><div><div>City: Austin
</div></div></div></div><div><div><div><div>State/Province: Texas
</div></div></div></div><div><div><div><div>Posting Start Date: 5/6/26
</div></div></div></div><div><div><div><div>Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients&rsquo; most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.
</div></div></div></div><div><div><div><div>Job Description:
<div><div><div><h2 class="jobSectionHeader"><b>Job Description
</b></h2></div><div><p>Job Description: Data Fabric verification engineer: 5 to 20 years of experience
<br>
<br>
PREFERRED EXPERIENCE:
<br>
Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes.
<br>
Exposure to RTL design, software development, formal verification, or other related domains.
<br>
Good understanding of computer organization/architecture.
<br>
Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
<br>
<br>
KEY RESPONSIBLITIES:
<br>
Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design.
<br>
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.
<br>
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
<br>
Collaborate with architects, hardware engineers and multiple IP development groups.
<br>
Drive formal verification for the block and write formal properties and assertions to verify the design
<br>
Responsible for verification quality metrics like pass rates, code coverage and functional coverage
<br>
<br>
ACADEMIC CREDENTIALS:
<br>
Bachelors or Masters degree in computer engineering/Electrical Engineering preferred
</p></div></div></div></div></div></div></div><div><div><div><div>Mandatory Skills: VLSI HVL Verification .<br>
<p></p>Experience: 3-5 Years .<br>
<p></p>The expected compensation for this role ranges from $45,000 to $121,000 .<br>
<p></p>Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.<br>
<p></p>Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.<br>
<p></p>Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.<br>
<p></p>Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.</div></div></div></div></div><p></p>

Design Verification Engineer (Data Fabric Verification Engineer)

NVIDIA

<div><p>NVIDIA&rsquo;s HW team is seeking highly motivated Engineers to assist in developing and integrating AI capabilities into verification tasks. As part of this team, you will play a key role in improving verification flows and creating AI agents that boost efficiency across teams by deploying various verification techniques. You will build and maintain the core infrastructure needed to run these agents in production, ensuring smooth and effective performance. If you are passionate about the latest research and innovative technologies crafting LLM and generative AI, this role and team offer an exciting chance to lead modern advancements.</p><p></p><p><b>
What you'll be doing:</b></p><ul><li><p>
Play a key role in design, development, and deployment of high-performance agents&rsquo; frameworks and tools.</p></li><li><p>
Develop AI agents that process sizable codebases and bypass failures to support coding and debugging efforts.</p></li><li><p>
Collaborate with HW engineering teams to understand their specific needs and challenges and ensure our agent platform is well-suited to these needs.</p></li><li><p>
Develop and optimize retrieval and generation algorithms for enterprise data (text, code, and images) to build advanced AI applications.</p></li><li><p>
Stay ahead by engaging with the latest advancements in machine learning and AI to build brand new solutions.</p></li><li><p>
Integrate technology-based optimizations into existing tools and flows.</p></li><li><p>
Lead with purpose and maintain high-quality engineering practices that encourage others to achieve excellence.</p></li></ul><p></p><p><b>
What we need to see:</b></p><ul><li><p>
BS/MS/PhD or equivalent experience in CS/CE/EE/Mathematics.</p></li><li><p>
5+ years of relevant experience.</p></li><li><p>
Strong proficiency in agentic LLM Libraries/Technologies like LangChain, LangGraph, AutoGen, CrewAI, RAGs, vector databases, timely engineering, knowledge graphs, etc.</p></li><li><p>
Solid understanding of GPU/CPU architectures and builds.</p></li><li><p>
Strong analytical skills to solve complex problems.</p></li><li><p>
Knowledge of HW verification methodologies and techniques.</p></li><li><p>
Hands-on experience with Verilog/System Verilog HDLs, temporal logic assertions, and able to understand complex RTL quickly.</p></li><li><p>
Excellent command of scripting using Python.</p></li><li><p>
Excellent interpersonal skills, able to effectively collaborate and work with members of a distributed team.</p></li></ul><p></p><p><b>
Ways to stand out from the crowd:</b></p><ul><li><p>
Proven track record of integrating AI into hardware verification processes.</p></li><li><p>
Experience with innovative generative AI technologies.</p></li><li><p>
Demonstrated leadership in cross-functional team environments.</p></li><li><p>
Strong problem-solving abilities.</p></li><li><p>
Outstanding skills in optimizing AI algorithms for performance.</p></li></ul><p></p>
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.<p></p><div><div><div><div><div><div><div><p>
You will also be eligible for equity and benefits.</p></div></div></div></div></div></div></div><p></p>
Applications for this job will be accepted at least until April 17, 2026.<p></p><p>
This posting is for an existing vacancy.</p><p>
NVIDIA uses AI tools in its recruiting processes.</p><p></p>
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.</div><p></p>

AI for Design Engineer

Cisco

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.
<br><br>
<b>ASIC Engineer Part time Internship (1 year):</b><br>
Join the Cisco Common ASIC Group, a team responsible for developing the ASICs at the heart of Cisco's next-generation switching systems. These ASICs are becoming more general and programmable, moving beyond traditional high-speed packet forwarding. You will work with Cisco’s outstanding switching solution team, driving the integration of Nexus systems and ACI with software like OpenStack, Docker, and Open vSwitch, to empower our customers in building multi-tenant clouds. Every time you access the Internet, chances are, your data has passed through one of our switches.
<br><br>
<b>You impact:</b><br>
<ul>
<li>Assist in the development and maintenance of advanced test benches and verification environments using System Verilog and UVM.</li>
<li>Participate in the end-to-end verification process of complex ASIC design blocks.</li>
<li>Help create comprehensive test plans and coverage points to ensure robust verification.</li>
<li>Support the upgrade and refinement of test benches to integrate new features seamlessly.</li>
<li>Collaborate with cross-functional teams for thorough cross-block verification and top-level integration.</li>
</ul>
Minimum qualification
<br><br>
<ul>
<li>Currently in your final year pursuing a Bachelor's or Master's degree in Electrical& Electronics Engineering (EE) or Computer Engineering (CE).</li>
<li>Strong knowledge in Digital Design and ASIC flow.</li>
<li>Familiarity with System Verilog-based verification</li>
<li>Familiarity with UVM.</li>
</ul>
Preferred Qualifications
<br><br>
<ul>
<li>Self-driven mindset with a commitment to personal and professional development.</li>
<li>Eagerness to learn and a proactive approach to problem-solving.</li>
<li>Excellent team working skills, with the ability to collaborate effectively with colleagues across different functions.</li>
</ul>
Why Cisco?
<br>Be part of a company that's a leader in networking technology, with a dedication to innovation and excellence.
<br>Work in an environment that cultivates growth, learning, and teamwork.
<br>Enjoy opportunities for advancement and personal development.
<br>Benefit from a flexible work culture that accommodates your educational commitments.
<br><b>Note:</b> This part-time internship (18 hours per week) is an excellent stepping stone for those considering a career in ASIC Verification Engineering and offers a chance to work alongside experienced professionals in the field.
<br><br>
Why Cisco?
<br><br>
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
<br>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
<br>We are Cisco, and our power starts with you.

ASIC Engineer Part time Internship (1 year):

Siemens

<div><p>Siemens Digital Industries Software is a global leader in Electronic Design Automation (EDA) software, hardware, and design solutions. We partner with the world&rsquo;s leading producers of semiconductor microelectronic circuits and systems, enabling them to design and produce cutting-edge electronic products faster and more efficiently.</p><p>
We are expanding our HAV portfolio to develop next-generation high-speed interconnect solutions. We are looking for a highly talented and driven <b>Senior Staff Pre-Silicon Validation/Verification Lead </b>to drive system-level validation across emulation and FPGA prototyping platforms.
</p><p>This role focuses on leading system-level validation for interconnect solutions such as PCIe, CXL, NVMe, and UCIe across emulation and FPGA prototyping environments. You will define and execute robust verification strategies, ensuring high-quality delivery at both protocol and system levels. The position requires a strong hands-on technical foundation combined with leadership capabilities.
</p><h2 class="jobSectionHeader"><b>Responsibilities:</b></h2><ul><li>
Lead verification and validation activities for high-speed interconnect protocols (PCIe, CXL, NVMe, UCIe).
</li><li>Define and drive end-to-end pre-silicon verification strategies across simulation, emulation, and FPGA prototyping.
</li><li>Build and scale verification environments, integrating SystemC/UVM transactors, RTL monitors, BFMs, and full software stacks for HW/SW co-verification.
</li><li>Drive system-level validation, including performance, interoperability, and scalability analysis (latency, bandwidth, coherency, bottlenecks).
</li><li>Own regression strategy, including test planning, coverage tracking, and failure triage to ensure release quality.
</li><li>Develop and maintain scalable CI/CD pipelines and validation infrastructure for efficient execution.
</li><li>Ensure QA readiness through structured validation flows, coverage closure, and alignment with customer use cases.
</li><li>Lead deep debugging and root-cause analysis across RTL, protocol, and system-level issues.
</li><li>Collaborate with cross-functional teams (R&amp;D, PM, PE, AE) to ensure alignment and timely delivery.
</li><li>Mentor engineers, review designs and test plans, and drive high-quality verification sign-off.</li></ul><h2 class="jobSectionHeader"><b>
Required experience/skills</b></h2><ul><li>
Bachelor&rsquo;s or Master&rsquo;s degree in Electronics, Computer Engineering, or a related field.
</li><li>+8 years of experience in system-level testing and verification.
</li><li>Strong understanding of interconnect protocols (PCIe, CXL, NVMe, AXI, UCIe).
</li><li>Hands-on experience with emulation platforms (e.g., Veloce, Palladium, ZeBu) or FPGA prototyping.
</li><li>Expertise in SystemVerilog, SystemC, and HW/SW co-verification methodologies.
</li><li>Proficiency in C/C++, with experience in bare-metal testing and validation with Linux drivers or firmware.
</li><li>Solid understanding of CPU architecture, memory hierarchy, and concepts such as IOMMU, coherency, and virtualization.
</li><li>Strong debugging skills across RTL, protocol, and system-level interactions.
</li><li>Experience building scalable validation infrastructure, including CI/CD pipelines, regression, and automation (Python, Bash).
</li><li>Proven ability to define and execute verification strategies and lead technical initiatives.</li></ul><p>
We&rsquo;re Siemens. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow!</p><p>
Siemens is an equal opportunities employer and do not discriminate unlawfully on any grounds. We are committed to providing access and equal opportunity.</p></div>

Sr. Staff Pre-Silicon Validation/Verification Lead

Marvell Technology

<div>
 <strong>
  About Marvell
  <br/>
  <br/>
 </strong>
 Marvell&rsquo;s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
 <br/>
 <br/>
 At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
 <br/>
 <br/>
 <strong>
  Your Team, Your Impact
  <br/>
  <br/>
 </strong>
 Connectivity group is the industry leader in PHY devices for AI, cloud datacenter and enterprise infrastructure. Our devices today power the full range of network connectivity from the optics of the AI GPU boards to top of the rack optical fibers and active copper cables of the data centers and their fabrics. The Connectivity Verification Group works closely with Analog and Digital Design teams and Systems/DSP teams to incorporate and build models and testbench infrastructure for mixed signal designs and verify the digital and analog designs and micro-architectures against the system definition and requirements and also works closely with the Software team to set up the API building infrastructure and guidelines.
 <br/>
 <br/>
 <strong>
  What You Can Expect
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Learn how the connectivity devices are dramatically impacting the AI-ML hardware revolution and the datacenters
  </li>
  <li>
   Learn the state-of-the-art optical PHY module architecture and design for 1.6T and 3.2T
  </li>
  <li>
   Learn state of the art UVM and SystemVerilog-based verification environment
  </li>
  <li>
   Apply the knowledge of Object-Oriented programming and its application to UVM/SystemVerilog to build new features into the verification environment as well as the test suite
  </li>
  <li>
   Work closely with Design teams to bring up new design features and verify them
  </li>
  <li>
   Learn modern day techniques of formal verification as well as code and functional coverage
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  What We're Looking For
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Bachelor's Degree in Electrical Engineering or a related field
  </li>
  <li>
   College level coursework on Digital Logic Design using Verilog, Computer Architecture, Signals, Systems and basic Digital Signal Processing
  </li>
  <li>
   Basic knowledge of Electrical Circuit Analysis (a course in Analog Circuits is preferred)
  </li>
  <li>
   A course project involving Object Oriented Programming language such as C/C++ or Java
  </li>
  <li>
   A course project involving principles of Verilog/VHDL/System-Verilog
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  Expected Base Pay Range (USD)
  <br/>
  <br/>
 </strong>
 81,880 - 122,600, $ per annum
 <br/>
 <br/>
 The successful candidate&rsquo;s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
 <br/>
 <br/>
 <strong>
  Additional Compensation And Benefit Elements
  <br/>
  <br/>
 </strong>
 Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life&rsquo;s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
 <br/>
 <br/>
 All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
 <br/>
 <br/>
 Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
 <br/>
 <br/>
 <strong>
  Interview Integrity
  <br/>
  <br/>
 </strong>
 To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
 <br/>
 <br/>
 These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
 <br/>
 <br/>
 <strong>
  This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
  <br/>
  <br/>
 </strong>
</div>


Design Verification Engineer - Early Career

Amazon Web Services

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><p>
The Senior SoC Software DevOps Engineer role centers on enabling the rapid and reliable development of software for AWSs most advanced custom machine learning chips. This position is critical to supporting the Trainium and Inferentia families of silicon which power large scale AI training at AWS. The engineer will serve as the primary owner of infrastructure that directly affects how quickly software teams can iterate on code for both pre silicon simulation environments and post silicon production deployments. By building robust automation and tooling the role ensures that tape outs for new chips stay on schedule and that software is ready to function immediately when first silicon becomes available. This work has a direct impact on AWSs ability to deliver advanced ML infrastructure to its largest customers.<br>
<br>
This role operates at the intersection of hardware and software requiring deep expertise in infrastructure engineering to solve unique challenges such as coordinating releases across isolated environments and validating firmware on real silicon. It is a foundational position for the SoC software teams as it frees engineers from infrastructure burdens allowing them to focus on feature development. Success in this role will be measured by improvements in development velocity release quality and the stability of systems that support multiple teams. The position demands a proactive approach to identifying bottlenecks and a strong ability to operate within novel technical contexts without prior domain knowledge in machine learning or chip design.<br>
<br>
Key job responsibilities<br>
The engineer will own the end to end CI/CD pipelines and release processes for all SoC software components including firmware hardware abstraction layers and modeling tools. This involves designing maintaining and evolving systems that produce reliable releases for both internal verification teams and external AWS services. A key task is ensuring these pipelines function across heterogeneous environments such as Corp networks and VPC. The role requires building qualification workflows that guarantee software meets strict quality standards before reaching customers or verification teams.<br>
<br>
Another core duty is developing hardware in the loop test infrastructure that validates SoC software on actual silicon in laboratory and automated testing settings. This includes creating frameworks to run tests on real chips simulate pre silicon environments and integrate results into continuous integration workflows. Additionally the engineer must build observability tools such as dashboards that track build health test coverage and pipeline performance along with alerting systems that notify teams of regressions. A significant focus will be on identifying and removing friction in development workflows such as slow build times or complex release steps using data driven insights to prioritize improvements that accelerate team productivity. The role also involves solving novel problems like bridging disconnected environments and orchestrating synchronized releases across multiple domains.<br>
<br>
About the team<br>
We're part of the SoC Software organization within Annapurna Labs (AWS). Our three software teams &mdash; uCode, HAL (Hardware Abstraction Layer), and Modeling &mdash; build the firmware, drivers, and virtual platforms for AWS's custom ML accelerator chips. We operate like a startup: small teams, high ownership, direct impact on AWS's most strategic silicon programs. This DevOps engineer will work across all three teams, with a mandate to improve velocity, quality, and developer experience for the entire SoC software organization.<br>
<br>
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we're building an environment that celebrates knowledge-sharing and mentorship.</p><h2 class="jobSectionHeader"><b>
BASIC QUALIFICATIONS</b></h2><ul><li>7+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience</li><li>Experience as a mentor, tech lead or leading an engineering team</li><li>Experience programming in Python and at least one of: Bash, Go, C++, or Java</li><li>Experience with infrastructure-as-code (CDK, CloudFormation, Terraform, etc.)</li><li>Experience with AWS services (Lambda, S3, EC2, CloudWatch, IAM, Secrets Manager, etc.)</li><li>Experience with Linux-based build and development environments</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Bachelor's degree in computer science or equivalent</li><li>Experience with Amazon's internal build and release systems (Brazil, Pipelines, CRUX, Apollo, etc.)</li><li>Experience building cross-environment or cross-account automation (e.g., bridging corporate and isolated/air-gapped environments)</li><li>Experience with Jenkins pipeline development and administration</li><li>Experience with hardware-in-the-loop testing or supporting hardware/silicon development teams</li><li>Experience building observability infrastructure: dashboards, metrics pipelines, alerting (CloudWatch, QuickSight, or similar)</li></ul><br>
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.<br>
<br>
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.<br>
<br>
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.<p><br>
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life &amp; AD&amp;D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.</p><br>
USA, CA, Cupertino - 193,300.00 - 261,500.00 USD annually<br>
USA, TX, Austin - 168,100.00 - 227,400.00 USD annually</div><p></p>

Senior Software Engineer - SoC DevOps, MLA-MI - Annapurna Labs

Renesas

<div><div><p><b>Job Description</b></p><p><br>
We are looking for a Senior AMS Verification Engineer to join our team based in Istanbul.</p><ul><li>
Lead verification planning and execution at the block and full-chip level.</li><li>
Work closely with architects and designers to align verification goals with design intent and architectural requirements.</li><li>
Drive enhancements in verification methodology while mentoring and supporting team members&rsquo; development.</li><li>
Develop event driven models for analog IC components and verify them.</li></ul><p><b><br>
Qualifications</b></p><br>
<ul><li>
MSEE with 10+ years or PhD with 7+ years of verification experience. Advanced knowledge of SystemVerilog and UVM methodology.</li><li>
Understanding both power management and related auxiliary circuitry: switching converters, linear converters, reference circuitry, bandgaps, data converters, and/or clock generators.</li><li>
Hands-on experience with verification methodologies and tools, including simulation, waveform analysis, execution automation, coverage collection, and gate-level simulations.</li><li>
Experience in Event Driven Modelling/Verification is a plus.</li><li>
Knowledge of scripting languages (Perl, Python, Tcl) is a plus.</li><li>
Fluent in English, clear written and verbal communications, including code documentation.</li></ul><p><b><br>
Additional Information</b></p><div></div><p><br>
Renesas is an embedded semiconductor solution provider driven by its Purpose &lsquo;<b>To Make Our Lives Easier</b>.&rsquo; As the industry&rsquo;s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog &amp; Connectivity, and Power.<br>
<br>
With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, &lsquo;<b>To Make Our Lives Easier</b>.&rsquo;<br>
<br>
At Renesas, you can:</p><ul><li><b>
Launch and advance your career </b>in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.</li></ul><ul><li><b>
Make a real impact </b>by developing innovative products and solutions to meet our global customers' evolving needs and help make people&rsquo;s lives easier, safe and secure.</li></ul><ul><li><b>
Maximize your performance and wellbeing</b> in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.</li></ul><p>
Are you ready to own your success and make your mark?</p><p>
Join Renesas. Let&rsquo;s <b>Shape the Future </b>together.</p><p>
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our <b>Diversity &amp; Inclusion Statement</b>.</p><p>
We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.</p></div></div>
<br><div><div><div><div><div><b>Job title</b></div><div>
Senior AMS Verification Engineer
</div></div></div><div><div><ul><li><div><b>Department
</b></div>Manufacturing
</li></ul><ul><li><div><b>Location
</b></div>Istanbul
</li></ul><ul><li><div><b>Remote
</b></div>No
</li></ul></div></div><div><div><div><b>Requisition ID
</b></div><div>20026426_2026-04-15</div></div></div></div></div><p></p>

Senior AMS Verification Engineer

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