layout engineer

Siliciom Technologies

<div></div><div><div><div><ul><li>ASIC</li><li>
Location: Bangalore</li><li>
Experience: 3 - 5 Years</li></ul><h5 class="jobSectionHeader"><b>
Required Skills &amp; Knowledge:</b></h5><ul><li>
Btech/Mtech Electronics/Electrical engineering</li><li>
Experience in Analog Mixed-signal layout and verification of high-speed digital and/or DDR IOs, Critical signal inclusion.</li><li>
Advanced understanding of Deep submicron effects and mitigation.</li><li>
Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies.</li><li>
Solid understanding of CMOS and FinFETlayouts and process technology in 28nm and smaller.</li><li>
Good understanding of basic ESD and latchup layout design considerations.</li><li>
Familiarity with ASIC physical design flow:LEF generation, Place &amp; Route &amp; understanding of top level verification flow, DRC/LVS, LPE.</li><li>
Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc</li><li>
Scripting skills for layout automation is a plus</li><li>
emote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership.</li><li>
Excellent written and verbal communication skills in interactions with customers, and internal development teams.</li></ul><p>
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com</p></div></div></div>

Analog Layout Engineer:

<p></p><div><p><b>Job ID</b> 2026-16571</p>
<p><b>Date posted</b> Feb. 23, 2026</p>
<p><b>Location</b> Bengaluru, India
</p><p><b>Category</b> Hardware Engineering</p></div><p></p>
<br><div><p>The engineer will assist in the definition, design, and verification of our package designs. The candidate needs to be able to adapt quickly to loosely defined problems and adapt to changes is important.</p><ul><li>
Layouts using best-known practices for DFM, DFA, Signal and Power Delivery Networks</li><li>
Work with minimal supervision and approach challenges with enthusiasm and persistence</li><li>
Bring forward ideas to improve overall team efficiency</li><li>
Communicate and coordinate with external vendors as necessary</li></ul><p><b>
Required Skills and Experience :</b></p><ul><li>
An Electrical Engineering degree or equivalent</li><li>
Experience with 2.5D and 3D package systems and their SI/PI requirements</li><li>
7+ years of recent experience in the use of Cadence APD &amp; Allegro toolsets</li><li>
Facilitate standardization by being aware of the bigger picture, including design features which will drive standardization and improve efficiency throughout the department</li></ul><p><b>
&ldquo;Nice To Have&rdquo; Skills and Experience :</b></p><ul><li>
Familiarity with EDA vendor collaboration, tool evaluation, and issue resolution</li><li>
Strong verbal, written communication and presentation skills</li><li>
Programming experience in Python, SKILL, or TCL Able to optimize design methodologies in packaging design</li></ul><p><i>
Our </i><b>10x mindset </b><i>guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work:</i>https://careers.arm.com/en/10x-mindset</p><div><div><div><div><div><div><div><div><div><div><p><br>
#LI-RS4</p></div></div></div></div></div></div></div></div></div></div><p></p><p>
Accommodations at Arm</p><p>
At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.</p><p>
Hybrid Working at Arm</p><p>
Arm&rsquo;s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team&rsquo;s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.</p><p>
Equal Opportunities at Arm</p><p>
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don&rsquo;t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.</p></div>

Senior Package Layout Engineer

Movandi Corporation

<div><p>Movandi&rsquo;s RFIC team develops advanced integrated circuits for 5G as well as SATCOM applications. As an RF IC Layout Engineer, you will be part of a key team designing highly sophisticated mm-Wave transceiver products. Responsibilities would include layout and verification of circuits such as Bandgap bias circuits, LDOs, amplifiers, VCOs, mixers, frequency multipliers/dividers, ADCs, etc. using industry standard tools Cadence, PVS, Calibre, etc.</p><p><b>
Requirements</b></p><ul><li>
Bachelor&rsquo;s degree in Electrical Engineering preferred, and/or 3+ years related industry experience.</li><li>
Must have effective interpersonal, teamwork, and communication skills</li><li>
Must have the ability to multi-task in a fast-paced dynamic environment</li><li><div><div><div><div><div><div><div><div><p>
Applicants must hold Saudi Arabian citizenship.</p></div></div></div></div></div></div></div></div></li></ul><div></div><p><b><br>
Key Skills</b></p><ul><li>
Hands-on experience in laying out analog/RF circuits such as: RX/TX sub-blocks, PLLs, Bandgap bias circuits, regulators, and other analog/RF circuits.</li><li>
Preferably experienced in mmWave RF ICs 20-40GHz or higher.</li><li>
Preferably experienced in Global Foundries SiGe and/or FDX processes. TSMC sub-micron CMOS technologies.</li><li>
Able to manage floorplan from unit cells, to block levels, to top level.</li><li>
Strong knowledge of Cadence, PVS, Calibre tools. Unix and Skill experience helpful.</li><li>
Strong knowledge on IC layout techniques for high frequency design. Parasitics, Coupling, EMIR, IR Drop, Symmetry.</li><li>
Able to troubleshoot and solve LVS DRC ERC errors.</li><li>
English oral and written communication skills required</li></ul></div>

Graduate Software Engineer

NVIDIA

<div><div>NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life&rsquo;s work , to amplify human creativity and intelligence. As an NVIDIAN, you&rsquo;ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!</div><div></div><div>
We are looking for a Senior Memory Mask Design Engineer &ndash; someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs.</div><div></div><div>
What you'll be doing:</div><ul><li><div>
Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.</div></li><li><div>
Deliver layouts for Full Custom Memory group specializing in digital Memory circuits.</div></li><li><div>
IP layout will comprise of significant digital components.</div></li><li><div>
Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts</div></li><li><div>
Follow company procedures and practices for IC layout activities.</div></li></ul><div></div><div>
What we need to see:</div><ul><li><div>
B.E/B Tech. / M Tech in Electronics or equivalent experience with 5+ Years of proven experience in Memory layout in advanced CMOS process.</div></li><li><div>
Detailed knowledge of industry standard EDA tools for Cadence.</div></li><li><div>
Experience with layout of high-performance memories of various types.</div></li><li><div>
Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)</div></li><li><div>
Experience with floor planning, block level routing and macro level assembly.</div></li><li><div>
Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.</div></li></ul><div></div><div>
We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status</div><div></div><div>
#LI-Hybrid</div></div><div></div>

Senior Memory Mask Designer

Marvylogic

<ul><li>Strong hands-on expertise in <b>Cadence Virtuoso LayoutXL</b>.</li><li>Must have solid command of <b>Mentor Calibre</b> (DRC, LVS, extraction, post-layout sims).</li><li>Extensive experience in <b>PAD Ring</b> and <b>Chip-Top integration</b>.</li><li>Good to have deep understanding of <b>DFM principles</b> and layout optimization.</li><li>Proven track record in <b>high-speed SERDES, RF, and/or PMIC layouts</b>.</li><li>Minimum <b>10+ years of analog layout experience</b>, with at least <b>3+ years in a leadership/managerial role</b>.</li></ul><p>Job Types: Full-time, Permanent</p><p>Pay: ₹1,500,000.00 - ₹2,000,000.00 per year</p><p>Benefits:</p><ul><li>Health insurance</li><li>Life insurance</li><li>Paid sick time</li><li>Paid time off</li><li>Provident Fund</li></ul><p>Work Location: In person</p>

Analog Layout Lead

Synopsys

<div><div><b>We Are:</b></div><div>
Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.</div><div><b>
Apprenticeship Experience:</b><br>
 At Synopsys, Apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide&mdash;and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!</div><div><b>
Mission Statement:</b><br>
 Our mission is to fuel today&rsquo;s innovations and spark tomorrow&rsquo;s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive&mdash;both at work and beyond.</div><div><b>
What You&rsquo;ll Be Doing:</b></div><ul><li>
Support layout development of analog and mixed-signal CMOS layouts.</li><li>
Collaborate with layout engineers to understand schematics and implement corresponding layouts.</li><li>
Assist in resolving layout issues and participate in physical verification flows.</li><li>
Learn and follow standard layout methodologies, best practices, and tool flows.</li><li>
Coordinate with team members to ensure timely completion of layout tasks.</li></ul><div><b>
What You&rsquo;ll Need:</b></div><ul><li>
B.E./B.Tech in Electronics, Electrical, Instrumentation, ECE, EEE, VLSI, or related fields.</li><li>
 Fresh graduates from the class of 2024 or 2025 only.</li><li>
Not currently enrolled in any M-Tech programs or postgraduate diplomas.</li><li>
Not employed in any full-time positions at any company (limited internship experience is acceptable).</li><li>
Basic familiarity with CMOS layout techniques, design rules, and second-order layout effects.</li><li>
Strong working knowledge of MS Office Suite (Excel, Word, PowerPoint).</li><li>
Open to learning new tools, flows, and methodologies.</li><li>
Strong analytical thinking, good communication skills, and ability to work well in a team.</li></ul><div><b>
Key Program Facts:</b></div><ul><li><b>
Program Length:</b> 12 months apprenticeship program.</li><li><b>
Location:</b> Pune, India.</li><li><b>
Working Model:</b> In-office.</li><li><b>
Full-Time/Part-Time:</b> Full-time.</li><li><b>
Start Date:</b> March / April 2026.</li></ul></div>

Analog Layout Apprenticeship

YO IT CONSULTING

<div><p><b>Job Description</b></p>
<p><b>Title</b>: Sr. Layout Designer<br>
<b>Experience</b>: 10 to 15 years<br>
<b>Location</b>: USA - Austin (Austin, TX, five days a week.)</p>
<p><b>Visa Status :Will sponsor H1-B</b></p>
<p><b>Must Have:</b></p>
<ul><li>10+ years of industry experience in analog/mixed-signal layout design in advanced process nodes (2nm&ndash;16nm, preferably TSMC).</li></ul>
<ul><li>Proven track record designing layouts for high-speed ADC/DAC and SerDes circuits, with deep understanding of timing, matching, shielding, and electromigration considerations.</li></ul>
<ul><li>Hands-on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and solid understanding of schematic-to-layout (S2L) flow.</li></ul>
<ul><li>Experience with FinFET and/or Gate-All-Around (GAA) process technologies.</li></ul>
<ul><li>Strong understanding of analog layout techniques: current mirrors, differential pairs, resistors, capacitors, biasing, shielding, guard rings, and ESD structures.</li></ul>
<ul><li>Experience leading tape-outs, including design documentation, sign-off checks, and cross-team coordination.</li></ul>
<ul><li>Good communication skills, both written and oral. The ability to articulate their thought process, and lead junior members is important.On-site in Austin, TX, five days a week.</li></ul>
Masters in Electrical Engineering, Computer Engineering, or related field.
<p><b>Role And Responsibilities:</b></p>
<p>Own the physical layout design of high-performance ADC/DAC, SerDes, and analog/mixed-signal circuits across advanced nodes (2nm&ndash;16nm).</p>
<p>Plan, and implement layout design for high-speed, low-noise analog blocks, ensuring signal integrity, matching, symmetry, and optimal parasitics.</p>
<p>Closely Collaborate with circuit designers to achieve aggressive power, performance, and area (PPA) targets, while maintaining design-for-manufacturability (DFM) best practices.</p>
<p>Work with Cadence Virtuoso and Synopsys Verification tools [to perform layout design, verification, and integration.</p>
<p>Drive floorplanning and analog block partitioning, ensuring effective power grid design, guard ring placement, and substrate isolation techniques.</p>
<p>Partner with foundry and CAD teams to optimize design flows for TSMC FinFET and Gate-All-Around (GAA) process nodes.</p>
<p>Conduct LVS, DRC, ERC, and parasitic extraction (PEX) reviews and close layout verification loops.</p>
<p>Participate in top-level integration and tape-out, ensuring all layout data and GDS handoffs meet signoff requirements.</p>
<p>Provide technical mentorship to fellow engineers and help define layout design methodologies and automation improvements.</p>
<p>Minimum Qualifications</p>
<p>10+ years of industry experience in analog/mixed-signal layout design in advanced process nodes (2nm&ndash;16nm, preferably TSMC).</p>
<p>Proven track record designing layouts for high-speed ADC/DAC and SerDes circuits, with deep understanding of timing, matching, shielding, and electromigration considerations.</p>
<p>Hands-on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and solid understanding of schematic-to-layout (S2L) flow.</p>
<p>Experience with FinFET and/or Gate-All-Around (GAA) process technologies.</p>
<p>Strong understanding of analog layout techniques: current mirrors, differential pairs, resistors, capacitors, biasing, shielding, guard rings, and ESD structures.</p>
<p>Experience leading tape-outs, including design documentation, sign-off checks, and cross-team coordination.</p>
<p>Strong analytical, problem-solving, and communication skills.</p>
<p>Self-motivated engineer eager to work in a fast-paced start-up environment, adaptable to evolving project demands.[EF5]</p>
<p><b>Preferred Qualifications</b></p>
<p>Familiarity with Mentor/Siemens Calibre verification tools and scripting (Skill, Python, or Tcl) for layout automation.</p>
<p>Exposure to floorplanning and top-level chip integration for complex mixed-signal SoCs.</p>
<p>Experience optimizing for signal integrity, IR drop, and thermal effects in high-speed designs.</p></div>

Sr Layout Designer

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