rtl design engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
MTS SILICON DESIGN ENGINEER</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD&rsquo;s DDR IPs.</div><div></div><div><b><br>
THE PERSON:</b>
</div><div>Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutions&mdash;including RTL logic, firmware routines, and algorithmic flows&mdash;into AMD&rsquo;s system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards</li><li>
Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines
</li><li>Create and execute validation plans to verify the correctness and performance of calibration firmware and algorithms. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability
</li><li>Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem</li><li>
Develop clear and comprehensive documentation for calibration flows, firmware APIs, and algorithm behavior. Ensure alignment with JEDEC specifications and internal design guidelines
</li><li>Stay updated with emerging DDR technologies and calibration techniques. Propose and implement innovative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces</li></ul><div><b>
PREFERRED EXPERIENCE:</b></div><ul><li>
B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience</li><li>
Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges</li><li>
Circuit timing/STA, and practical experience with tools</li><li>
Working knowledge of C; embedded experience a plus</li><li>
Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards</li><li>
Been exposed to memory controller and PHYs from different IP vendors</li><li>
Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software</li><li>
Version control systems such as Perforce, ICManage or Git</li><li>
Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus</li><li>
Strong verbal and written communication skills</li><li>
Should have experience working in geographically dispersed team and should be a strong team player</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+ yrs of exp</li></ul><p></p><p><br>
#LI-SR4</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

Senior RTL Design Engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
MTS SILICON DESIGN ENGINEER</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
The focus of this role is to plan, build, and execute the deisgn and validation of new and existing features for AMD&rsquo;s DDR IPs.</div><div></div><div><b><br>
THE PERSON:</b>
</div><div>Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutions&mdash;including RTL logic, firmware routines, and algorithmic flows&mdash;into AMD&rsquo;s system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards</li><li>
Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines
</li><li>Create and execute validation plans to verify the correctness and performance of calibration firmware and algorithms. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability
</li><li>Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem</li><li>
Develop clear and comprehensive documentation for calibration flows, firmware APIs, and algorithm behavior. Ensure alignment with JEDEC specifications and internal design guidelines
</li><li>Stay updated with emerging DDR technologies and calibration techniques. Propose and implement innovative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces</li></ul><div><b>
PREFERRED EXPERIENCE:</b></div><ul><li>
B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience</li><li>
Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges</li><li>
Circuit timing/STA, and practical experience with tools</li><li>
Working knowledge of C; embedded experience a plus</li><li>
Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards</li><li>
Been exposed to memory controller and PHYs from different IP vendors</li><li>
Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software</li><li>
Version control systems such as Perforce, ICManage or Git</li><li>
Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus</li><li>
Strong verbal and written communication skills</li><li>
Should have experience working in geographically dispersed team and should be a strong team player</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+ yrs of exp</li></ul><p></p><p><br>
#LI-SR4</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

Lead RTL Design Engineer with Memory Technologies

Analog Devices

<div><div>Come join Analog Devices (ADI) &ndash; a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.</div><div></div><div>
ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.</div><div></div><div>
About Analog Devices</div><div>
Analog Devices, Inc. (NASDAQ: <div>ADI</div> ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible&trade;. Learn more at <div>www.analog.com</div> and on <div>LinkedIn</div> and <div>Twitter (X)</div>.</div><div></div><div><br>
Digital Design Engineer</div><div></div><div>
Main Responsibilities:</div><ul><li>
RTL Implementation of various SerDes design modules using SystemVerilog</li><li>
Unit level and top level testbench creations and verification</li><li>
Architecture development and design specifications</li><li>
Create and manage verification plans and regression tests</li><li>
Take part in all aspects of design success from conception to production</li><li>
Contribute to bench validation</li><li>
Work and collaborate effectively in a multi-cultural and multi-site environment</li></ul><div></div><div>
Preferred Qualifications:</div><ul><li>
BS or MS in Electronics Engineering with specialization in Digital IC Design</li><li>
Hand-on experience with ASIC and FPGA digital design, verification and product development methodologies</li><li>
Experience in high speed and low power RTL design and verification using Hardware Description Languages (preferably System Verilog)</li><li>
Experience with EDA tools form such as Synopsys, Cadence, Xilinx/AMD and Altera/Intel for ASIC and FPGA design</li><li>
Experience in synthesis, timing closure, linting, constrained and random verification, and logic equivalence checking</li><li>
Familiarity with UVM verification concepts</li><li>
Familiarity with digital signal processing and image processing concepts</li><li>
Strong analytical thinking and problem-solving skills</li><li>
Excellent written and verbal communication skills to work both independently and collaboratively as a part of a team</li><li>
Self-driven, motivated and passionate learner</li></ul><div></div><div><i>
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position &ndash; except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) &ndash; may have to go through an export licensing review process.</i></div><div></div><div><i>
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.</i></div><div></div>
Job Req Type: Graduate Job<br>
<div></div>
Required Travel: Yes, 10% of the time</div><div></div>

Engineer, Digital Design Engineering

NVIDIA

<div><p>We are now looking for a Senior ASIC Design Engineer - DFX</p><p></p><p>
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI &mdash; the next era of computing. NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life&rsquo;s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.</p><p></p><p><b>
What You&rsquo;ll Be Doing:</b></p><ul><li><p>
As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You&rsquo;ll help drive innovation across the full silicon lifecycle&mdash;from pre-silicon to post-silicon&mdash;while mentoring and collaborating with cross-functional teams.</p></li><li><p>
Own the architecture, design, and verification of DFT IPs for cutting-edge SoC designs.</p></li><li><p>
Develop, deploy, and enhance DFT methodologies for scalability and future product needs.</p></li><li><p>
Define and align feature sets by working closely with architects, platform, and software teams.</p></li><li><p>
Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.</p></li><li><p>
Create and execute test plans to support both functional and DFT full-chip verification.</p></li><li><p>
Support post-silicon bring-up and validation efforts including debug and issue resolution.</p></li><li><p>
Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.</p></li></ul><p></p><p><b>
What We need to see:</b></p><ul><li><p>
Master&rsquo;s degree (or equivalent experience) in Electrical Engineering or related field.</p></li><li><p>
5+ years of hands-on experience in SoC architecture, RTL design, and verification.</p></li><li><p>
Strong proficiency in micro-architecture and RTL development using Verilog.</p></li><li><p>
Experience with formal verification using JasperGold is a plus.</p></li><li><p>
Deep expertise in DFT design, methodology, and implementation.</p></li><li><p>
Familiarity with related domains such as clocking, STA, place &amp; route, and power optimization.</p></li><li><p>
Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.</p></li><li><p>
Proficiency in scripting languages such as Python, Perl, or Tcl.</p></li><li><p>
Excellent communication skills and a collaborative mindset&mdash;with a curiosity and passion for solving complex technical challenges.</p></li></ul><p></p><p>
This is your chance to join a high-impact team driving the foundation of next-generation semiconductor innovation. If you&rsquo;re passionate about DFT and SoC architecture, and want to work in a fast-paced, collaborative environment where your ideas make a difference&mdash;we&rsquo;d love to hear from you.</p><p></p>
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.<p></p><div><div><div><div><div><div><div><p>
You will also be eligible for equity and benefits.</p></div></div></div></div></div></div></div><p></p>
Applications for this job will be accepted at least until October 28, 2025.<p></p>
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.</div><p></p>

Senior ASIC Design Engineer - DFX

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
SMTS SILICON DESIGN ENGINEER</b><br>
<br>
<b>THE ROLE:</b></div><div>
As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.<br>
<br>
<b>THE PERSON:</b></div><div>
The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team.<br>
<br>
<b>KEY RESPONSIBLITIES:</b></div><ul><li>
Design of IP and subsystems with integration of AMD and other 3rd party IPs</li><li>
Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs</li><li>
Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC</li><li>
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up</li></ul><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
8-12 years full-time experience in IP hardware design</li><li>
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs</li><li>
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)</li><li>
Clock domain crossing (CDC) tools</li><li>
Detailed understanding of SoC design flows</li><li>
Understanding of IP/SS/SoC Power Management techniques &ndash; Power Gating, Clock Gating</li><li>
Experience with embedded processors and data fabric architectures (NoC)</li><li>
Outstanding interaction skills while communicating both written and verbally</li><li>
Ability to work with multi-level functional teams across various geographies</li><li>
Outstanding problem-solving and analytical skills</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors degree in Computer Engineering/Electrical Engineering plus 12 years full-time experience in IP hardware design, or Masters degree plus 8 years experience in same.</li></ul><p></p><p><br>
#LI-NS1</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

IP/ Subsystem Design Lead

Amazon Web Services

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><div>
Utility Computing (UC)<br>
AWS Utility Computing (UC) provides product innovations &mdash; from foundational services such as Amazon&rsquo;s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS&rsquo;s services and features apart in the industry. As a member of the UC organization, you&rsquo;ll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for customers who require specialized security solutions for their cloud services.<br>
<br>
Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago&mdash;even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.<br>
<br>
About AWS<br>
Amazon Web Services (AWS) is the world&rsquo;s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating &mdash; that&rsquo;s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.<br>
<br>
Diverse Experiences<br>
AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn&rsquo;t followed a traditional path, or includes alternative experiences, don&rsquo;t let it stop you from applying.
<br>
<br>
Work/Life Balance<br>
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there&rsquo;s nothing we can&rsquo;t achieve in the cloud.
<br>
<br>
Inclusive Team Culture<br>
Here at AWS, it&rsquo;s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness.<br>
<br>
Mentorship &amp; Career Growth<br>
We&rsquo;re continuously raising our performance bar as we strive to become Earth&rsquo;s Best Employer. That&rsquo;s why you&rsquo;ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
<br>
<br>
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.<br>
<br>
Key job responsibilities<br>
<ul><li>integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing</li><li>As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.</li><li>Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.</li><li>Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.</li><li>Perform lint and clock domain crossing quality checks on the design.</li></ul>
- Work with with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.<br>
<br>
You will thrive in this role if you:<br>
<ul><li>Are familiar with scripting in Python</li><li>Are proficient with assertions</li><li>Have good debug skills to analyze RTL test failures</li><li>Have a &quot;Learn and Be Curious&quot; mindset</li></ul><br>
About the team<br>
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.<br>
<br>
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we&rsquo;re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.</div><h2 class="jobSectionHeader"><b>
BASIC QUALIFICATIONS</b></h2><ul><li>BS degree in electrical engineering or equivalent</li><li>3+ years in RTL design for SOC</li><li>3+ years of VLSI engineering</li><li>3+ years with code quality tools including: Spyglass, LINT, or CDC</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Experience scripting for automation (e.g., Python, Perl, Ruby)</li><li>Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints</li><li>Familiarity with data path design, interconnects, AXI protocol</li><li>Good analytical, problem solving, and communication skills</li></ul><br>
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.<br>
<br>
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.<br>
<br>
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.<br>
<br>
Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $129,800/year in our lowest geographic market up to $212,800/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits. This position will remain posted until filled. Applicants should apply via our internal or external career site.</div>

ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><div>
Utility Computing (UC)<br>
AWS Utility Computing (UC) provides product innovations &mdash; from foundational services such as Amazon&rsquo;s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS&rsquo;s services and features apart in the industry. As a member of the UC organization, you&rsquo;ll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for customers who require specialized security solutions for their cloud services.<br>
<br>
Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago&mdash;even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.<br>
<br>
About AWS<br>
Amazon Web Services (AWS) is the world&rsquo;s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating &mdash; that&rsquo;s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.<br>
<br>
Diverse Experiences<br>
AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn&rsquo;t followed a traditional path, or includes alternative experiences, don&rsquo;t let it stop you from applying.
<br>
<br>
Work/Life Balance<br>
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there&rsquo;s nothing we can&rsquo;t achieve in the cloud.
<br>
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Inclusive Team Culture<br>
Here at AWS, it&rsquo;s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness.<br>
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Mentorship &amp; Career Growth<br>
We&rsquo;re continuously raising our performance bar as we strive to become Earth&rsquo;s Best Employer. That&rsquo;s why you&rsquo;ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
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Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.<br>
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Key job responsibilities<br>
<ul><li>integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing</li><li>As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.</li><li>Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.</li><li>Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.</li><li>Perform lint and clock domain crossing quality checks on the design.</li></ul>
- Work with with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.<br>
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You will thrive in this role if you:<br>
<ul><li>Are familiar with scripting in Python</li><li>Are proficient with assertions</li><li>Have good debug skills to analyze RTL test failures</li><li>Have a &quot;Learn and Be Curious&quot; mindset</li></ul><br>
About the team<br>
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.<br>
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Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we&rsquo;re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.</div><h2 class="jobSectionHeader"><b>
BASIC QUALIFICATIONS</b></h2><ul><li>Bachelor's degree in electrical engineering or equivalent</li><li>5+ years in RTL design for SOC</li><li>5+ years of VLSI engineering</li><li>5+ years with code quality tools including: Spyglass, LINT, or CDC</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Master's degree in electrical engineering, computer engineering, or equivalent</li><li>Experience scripting for automation (e.g., Python, Perl, Ruby)</li><li>Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints</li><li>Familiarity with data path design, interconnects, AXI protocol</li><li>Good analytical, problem solving, and communication skills</li></ul><br>
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.<br>
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Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.<br>
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Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.<br>
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Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits. This position will remain posted until filled. Applicants should apply via our internal or external career site.</div>

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

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