senior asic engineer

NVIDIA

<div><p>We are now looking for a Senior ASIC Design Engineer - DFX</p><p></p><p>
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI &mdash; the next era of computing. NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life&rsquo;s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.</p><p></p><p><b>
What You&rsquo;ll Be Doing:</b></p><ul><li><p>
As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You&rsquo;ll help drive innovation across the full silicon lifecycle&mdash;from pre-silicon to post-silicon&mdash;while mentoring and collaborating with cross-functional teams.</p></li><li><p>
Own the architecture, design, and verification of DFT IPs for cutting-edge SoC designs.</p></li><li><p>
Develop, deploy, and enhance DFT methodologies for scalability and future product needs.</p></li><li><p>
Define and align feature sets by working closely with architects, platform, and software teams.</p></li><li><p>
Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.</p></li><li><p>
Create and execute test plans to support both functional and DFT full-chip verification.</p></li><li><p>
Support post-silicon bring-up and validation efforts including debug and issue resolution.</p></li><li><p>
Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.</p></li></ul><p></p><p><b>
What We need to see:</b></p><ul><li><p>
Master&rsquo;s degree (or equivalent experience) in Electrical Engineering or related field.</p></li><li><p>
5+ years of hands-on experience in SoC architecture, RTL design, and verification.</p></li><li><p>
Strong proficiency in micro-architecture and RTL development using Verilog.</p></li><li><p>
Experience with formal verification using JasperGold is a plus.</p></li><li><p>
Deep expertise in DFT design, methodology, and implementation.</p></li><li><p>
Familiarity with related domains such as clocking, STA, place &amp; route, and power optimization.</p></li><li><p>
Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.</p></li><li><p>
Proficiency in scripting languages such as Python, Perl, or Tcl.</p></li><li><p>
Excellent communication skills and a collaborative mindset&mdash;with a curiosity and passion for solving complex technical challenges.</p></li></ul><p></p><p>
This is your chance to join a high-impact team driving the foundation of next-generation semiconductor innovation. If you&rsquo;re passionate about DFT and SoC architecture, and want to work in a fast-paced, collaborative environment where your ideas make a difference&mdash;we&rsquo;d love to hear from you.</p><p></p>
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.<p></p><div><div><div><div><div><div><div><p>
You will also be eligible for equity and benefits.</p></div></div></div></div></div></div></div><p></p>
Applications for this job will be accepted at least until October 28, 2025.<p></p>
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.</div><p></p>

Senior ASIC Design Engineer - DFX

Amazon Web Services

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><div>
Utility Computing (UC)<br>
AWS Utility Computing (UC) provides product innovations &mdash; from foundational services such as Amazon&rsquo;s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS&rsquo;s services and features apart in the industry. As a member of the UC organization, you&rsquo;ll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for customers who require specialized security solutions for their cloud services.<br>
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Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago&mdash;even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.<br>
<br>
About AWS<br>
Amazon Web Services (AWS) is the world&rsquo;s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating &mdash; that&rsquo;s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.<br>
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Diverse Experiences<br>
AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn&rsquo;t followed a traditional path, or includes alternative experiences, don&rsquo;t let it stop you from applying.
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Work/Life Balance<br>
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there&rsquo;s nothing we can&rsquo;t achieve in the cloud.
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Inclusive Team Culture<br>
Here at AWS, it&rsquo;s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness.<br>
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Mentorship &amp; Career Growth<br>
We&rsquo;re continuously raising our performance bar as we strive to become Earth&rsquo;s Best Employer. That&rsquo;s why you&rsquo;ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
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Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.<br>
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Key job responsibilities<br>
<ul><li>integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing</li><li>As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.</li><li>Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.</li><li>Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.</li><li>Perform lint and clock domain crossing quality checks on the design.</li></ul>
- Work with with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.<br>
<br>
You will thrive in this role if you:<br>
<ul><li>Are familiar with scripting in Python</li><li>Are proficient with assertions</li><li>Have good debug skills to analyze RTL test failures</li><li>Have a &quot;Learn and Be Curious&quot; mindset</li></ul><br>
About the team<br>
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.<br>
<br>
Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we&rsquo;re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.</div><h2 class="jobSectionHeader"><b>
BASIC QUALIFICATIONS</b></h2><ul><li>Bachelor's degree in electrical engineering or equivalent</li><li>5+ years in RTL design for SOC</li><li>5+ years of VLSI engineering</li><li>5+ years with code quality tools including: Spyglass, LINT, or CDC</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Master's degree in electrical engineering, computer engineering, or equivalent</li><li>Experience scripting for automation (e.g., Python, Perl, Ruby)</li><li>Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints</li><li>Familiarity with data path design, interconnects, AXI protocol</li><li>Good analytical, problem solving, and communication skills</li></ul><br>
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.<br>
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Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.<br>
<br>
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.<br>
<br>
Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits. This position will remain posted until filled. Applicants should apply via our internal or external career site.</div>

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Microsoft

<div><p>Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft&rsquo;s expanding Cloud Infrastructure and responsible for powering Microsoft&rsquo;s &ldquo;Intelligent Cloud&rdquo; mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.</p><p>
The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives.</p><p>
We are seeking a Senior Software Engineer to join our DPU Runtime Operating System team responsible for developing cutting edge, high-performance, scalable and programmable DPU software. We seek a system generalist that will focus on developing high performance operating systems and runtime components, supporting software, tools, and processes.</p><p>
You will be spearheading efforts within our DPU Confidential Compute team, focusing on the development, maintenance, and review of software for the creation and integration of security features, , in-service software update services (ISSU), to enable our next-generation of confidential compute and advanced update capabilities.</p><p>
You will bring your operating systems, and embedded development experience to contribute to DPU driver code and related host software and support. Your contributions will have a wide impact across Azure through the development of the latest generation DPU-based products.</p><h2 class="jobSectionHeader"><b>
Responsibilities</b></h2><ul><li>
Architect and design firmware and software for the DPU Runtime Operating System</li><li>
Develop firmware update middleware and operating system capabilities.</li><li>
Develop, maintain and debug DPU issues, with a productivity boosting mindset.</li><li>
Design and implement improvements to make development and production debugging easier.</li><li>
Participate in code reviews and provide feedback to other developers.</li><li>
Work closely with both Software and ASIC teams on co-development of next generation Silicon.</li></ul><h2 class="jobSectionHeader"><b>
Qualifications</b></h2><p>
Required</p><ul><li>
8+ years of C/C++ programming experience</li><li>
3+ years of Computer Architecture and Operating Systems experience, with contributions to operating systems kernels, drivers, or other software.</li><li>
3+ years of broad systems generalist experience with demonstrated initiative in working beyond core competencies to solve problems, address defects, and enhance productivity.</li></ul><p>
Preferred</p><ul><li>
1+ years of experience leveraging AI technologies to boost personal or team productivity.</li><li>
Experience with simulation and emulation</li><li>
Experience with deploying Software and/or Platforms at scale</li></ul><p></p><p><br>
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.</p><br>
<div></div>
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.</div>

Senior Software Engineer

<div>
 Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft&rsquo;s expanding Cloud Infrastructure and responsible for powering Microsoft&rsquo;s &ldquo;Intelligent Cloud&rdquo; mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.
 <br/>
 <br/>
 The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives.
 <br/>
 <br/>
 We are seeking a Senior Software Engineer/Senior DevOps Engineer to join our DPU and associated tools. You will be a key contributor within our DPU team. You will bring your Operating System, Driver, and Embedded Software Development experience to contribute to DPU software. Your contributions will have a wide impact across Azure through the development of the latest generation PCIe adapter cards.
 <br/>
 <br/>
 <strong>
  Responsibilities
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   As a DPU Build&amp;Tools Engineer you will be responsible for the following:
  </li>
  <li>
   Build Infra
  </li>
  <li>
   Develop and maintain build and test infrastructure.
  </li>
  <li>
   Plan for longer-term requirements for both build hardware and access to prototype and working Azure systems
  </li>
  <li>
   Help team move existing build and test infrastructure toward Azure processes and platforms while keeping existing hardware and software development making rapid progress
  </li>
  <li>
   Test infra
  </li>
  <li>
   Develop and maintain test infrastructure that allows DPU engineers to test their code on emulators and pre-production silicon/systems
  </li>
  <li>
   Keep test infrastructure and machine fleets running while continuously improving reliability and reducing maintenance burden
  </li>
  <li>
   Work with engineering teams to identify future requirements for infrastructure, machines, and test frameworks
  </li>
  <li>
   Develop test-related tooling, frameworks, and automation that improves developer productivity
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  Qualifications
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   Bachelor's Degree in Computer Science, or related technical discipline AND 4+ years technical engineering experience with coding in languages including, but not limited to, Python. Familiarity with C/C++.
  </li>
  <li>
   OR equivalent experience.
  </li>
  <li>
   3+ years of experience working with software build, build pipelines and processes (build and release mgmt). C/C++
  </li>
  <li>
   2+ years of experience with embedded systems
  </li>
  <li>
   1+ years of experience with web and REST (Application Programming Interface) APIs apps
  </li>
  <li>
   3+ years of experience working in projects related to tooling, automation and test frameworks/infrastructure, in a SWE capacity.
   <br/>
   <br/>
  </li>
 </ul>
 <strong>
  Preferred
  <br/>
  <br/>
 </strong>
 <ul>
  <li>
   2+ years of experience in OS kernel building, driver building
  </li>
  <li>
   2+ years of experience in automating infrastructure (on-prem, cloud)
  </li>
  <li>
   1+ years of experience in monitoring&amp;logging systems
  </li>
  <li>
   Knowledge of networking, storage, embedded systems, or operating systems (Windows, Linux)
  </li>
  <li>
   Knowledge and familiarity with containerized, virtualized environments.
  </li>
  <li>
   Knowledge and experience with distributed systems
  </li>
  <li>
   Experience with Operating System (Linux or Windows) configuration and deployment
  </li>
  <li>
   Experience with ARM architecture
   <br/>
   <br/>
  </li>
 </ul>
 #GTA #SCHIEINDIA
 <br/>
 <br/>
 Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
 <br/>
 <br/>
 Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
</div>


Analog Devices

<div><div>Come join Analog Devices (ADI) &ndash; a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.</div><div></div><div>
ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.</div><div></div><div>
About Analog Devices</div><div>
Analog Devices, Inc. (NASDAQ: <div>ADI</div> ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible&trade;. Learn more at <div>www.analog.com</div> and on <div>LinkedIn</div> and <div>Twitter (X)</div>.</div><div></div><div><br>
Digital Design Engineer</div><div></div><div>
Main Responsibilities:</div><ul><li>
RTL Implementation of various SerDes design modules using SystemVerilog</li><li>
Unit level and top level testbench creations and verification</li><li>
Architecture development and design specifications</li><li>
Create and manage verification plans and regression tests</li><li>
Take part in all aspects of design success from conception to production</li><li>
Contribute to bench validation</li><li>
Work and collaborate effectively in a multi-cultural and multi-site environment</li></ul><div></div><div>
Preferred Qualifications:</div><ul><li>
BS or MS in Electronics Engineering with specialization in Digital IC Design</li><li>
Hand-on experience with ASIC and FPGA digital design, verification and product development methodologies</li><li>
Experience in high speed and low power RTL design and verification using Hardware Description Languages (preferably System Verilog)</li><li>
Experience with EDA tools form such as Synopsys, Cadence, Xilinx/AMD and Altera/Intel for ASIC and FPGA design</li><li>
Experience in synthesis, timing closure, linting, constrained and random verification, and logic equivalence checking</li><li>
Familiarity with UVM verification concepts</li><li>
Familiarity with digital signal processing and image processing concepts</li><li>
Strong analytical thinking and problem-solving skills</li><li>
Excellent written and verbal communication skills to work both independently and collaboratively as a part of a team</li><li>
Self-driven, motivated and passionate learner</li></ul><div></div><div><i>
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position &ndash; except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) &ndash; may have to go through an export licensing review process.</i></div><div></div><div><i>
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.</i></div><div></div>
Job Req Type: Graduate Job<br>
<div></div>
Required Travel: Yes, 10% of the time</div><div></div>

Engineer, Digital Design Engineering

Amazon.com

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><div>
As a Senior Design Verification Engineer, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms.<br>
<br>
You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:
<br>
<br>
<ul><li>Architect and implement verification environments for complex functional blocks
</li><li>Create and enhance verification environments using SystemVerilog and UVM
</li><li>Develop comprehensive test plans through collaboration with design engineers, SW and architects
</li><li>Implement coverage measures for stimulus and corner-case scenarios</li><li>Participate in test plan and coverage reviews</li><li>Drive complex RTL and TB debugs</li><li>Drive UPF based low power verification</li><li>Contribute to verification activities across simulation and emulation platforms</li><li>Work on creating the automation scripts to support DV methodologies</li><li>Create infrastructure to performs system level performance analysis<br>
</li></ul></div><h2 class="jobSectionHeader"><b>BASIC QUALIFICATIONS</b></h2><ul><li>Bachelor's degree in Electrical Engineering or a related field</li><li>Knowledge of hardware platforms</li><li>Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing</li><li>Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing</li><li>Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design</li><li>Experience with industry standard tools and scripting languages (Python or Perl) for automation</li><li>Experience in object-oriented design skills</li><li>10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks</li><li>Experience with RTL development environments</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Master's degree or Ph.D. degree in Electrical Engineering or related field</li><li>Experience with ARM and various DSP ISAs</li><li>Experience in system-level debugging</li><li>Experience with transaction level modeling</li><li>Knowledge of SoC architecture</li><li>Experience communicating technical details verbally and in writing</li><li>Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols</li><li>Experience with formal verification methods Experience with Low power verification methods</li><li>Experience with Baremetal processor environments</li><li>Familiarity with industry standard I/O interfaces</li><li>FPGA and emulation platform knowledge</li></ul><br>
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.</div>

Senior Design Verification Engineer, HW Compute Group

Marvell Technology

<div><div>About Marvell</div><div>
Marvell&rsquo;s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.</div><div></div><div>
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.</div><div></div><div>
Your Team, Your Impact</div><div></div>
As a Product Engineer Intern, you&rsquo;ll join a high-performing team working on advanced semiconductor technologies. You&rsquo;ll collaborate with ASIC Design, Applications, and Test Engineering teams to develop, debug, and optimize test solutions for complex ASIC products. Your work will span the full product lifecycle, with a strong focus on data-driven infrastructure supporting yield, quality, and reliability.<div></div><div>
What You Can Expect</div><ul><li>
Support silicon bring-up and validate new device features and test methodologies</li><li>
Analyze wafer sort and final test data to assess product performance</li><li>
Troubleshoot and resolve Product, Test engineering issues</li><li>
Drive yield and test time improvements through data analysis and root-cause investigation</li><li>
Build automated dashboards and tools for engineering insights</li><li>
Use Python , VBA and JMP for statistical analysis and correlation studies</li></ul><div></div><div>
What We're Looking For</div><ul><li>
Currently pursuing a Bachelor&rsquo;s or Master&rsquo;s in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related discipline.</li><li>
Completed relevant coursework in semiconductor engineering, including digital electronics, analog electronics, and VLSI design.</li><li>
Solid understanding of circuit theory, Semiconductor Device Physics, and programming (Python/C/C++/VBA).</li><li>
Strong analytical, communication, and collaboration skills.</li><li>
Detail-oriented, proactive, and accountable.</li><li>
Comfortable operating in a fast-paced, dynamic, and multitasking environment.</li></ul><div></div><div>
Expected Base Pay Range (USD)</div>
22 - 45, $ per hour.<div></div><div>
The successful candidate&rsquo;s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.</div><div></div><div>
Additional Compensation and Benefit Elements</div>
For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness &amp; mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.<div></div><div>
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.</div><div></div><div>
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at <div>TAOps@marvell.com</div>.</div><div></div><div><i>
Interview Integrity</i></div><div><i><br>
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.</i><br>
<br>
<i>Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.</i></div><div></div><div>
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.</div><div></div>
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