silicon design engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
MTS SILICON DESIGN ENGINEER</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
The position will involve working with a very experienced circuit design team of CPU core macros and is responsible for delivering the macro design to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology.</div><div></div><div><b><br>
THE PERSON:</b></div><div>
Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Good Understanding of SRAM, ROM and digital circuit design</li><li>
Implementing Design Schematic</li><li>
Circuit design and debug</li><li>
Silicon issue debug
</li><li>Statistical analysis of design</li><li>
Logical equivalence check of design</li><li>
Handling Internal timings, Power, Leakage, Crosstalk Analysis(noise), Electromigration, IR drop</li><li>
Handling different design tools &ndash; Cadence Virtuoso, Formality, ESP-CV, NanoTime, Hspice, StarRC, Mentor Graphics Calibre</li></ul><div><b>
PREFERRED EXPERIENCE:</b></div><ul><li>
7+ years of professional experience in SRAM/ROM design, preferably with high performance memory circuit designs.</li><li>
Experience in high-speed SRAM design, mainly L1, L2 and L3 cache memory macro design</li><li>
Experience in checks for logic equivalence</li><li>
Versatility with scripts to automate design flow.</li><li>
Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams</li><li>
Experience in FinFET/GAA &amp; Dual Patterning nodes such as 5/3/2nm</li><li>
Good layout understanding.</li><li>
Good understanding of computer organization/architecture is preferred.</li><li>
Strong analytical/problem solving skills and pronounced attention to details.</li></ul><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Qualification: Bachelors or Masters in Electrical/Electronics Engineering</li></ul><p>
#LI-RR1<br>
#LI-Hybrid</p><br>
<div></div>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

Sram/Circuit Design Lead

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
SMTS SILICON DESIGN ENGINEER</b><br>
<br>
<b>THE ROLE:</b></div><div>
As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.<br>
<br>
<b>THE PERSON:</b></div><div>
The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team.<br>
<br>
<b>KEY RESPONSIBLITIES:</b></div><ul><li>
Design of IP and subsystems with integration of AMD and other 3rd party IPs</li><li>
Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs</li><li>
Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC</li><li>
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up</li></ul><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
8-12 years full-time experience in IP hardware design</li><li>
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs</li><li>
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)</li><li>
Clock domain crossing (CDC) tools</li><li>
Detailed understanding of SoC design flows</li><li>
Understanding of IP/SS/SoC Power Management techniques &ndash; Power Gating, Clock Gating</li><li>
Experience with embedded processors and data fabric architectures (NoC)</li><li>
Outstanding interaction skills while communicating both written and verbally</li><li>
Ability to work with multi-level functional teams across various geographies</li><li>
Outstanding problem-solving and analytical skills</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors degree in Computer Engineering/Electrical Engineering plus 12 years full-time experience in IP hardware design, or Masters degree plus 8 years experience in same.</li></ul><p></p><p><br>
#LI-NS1</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

IP/ Subsystem Design Lead

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
MTS SILICON DESIGN ENGINEER</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD&rsquo;s DDR IPs.</div><div></div><div><b><br>
THE PERSON:</b>
</div><div>Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutions&mdash;including RTL logic, firmware routines, and algorithmic flows&mdash;into AMD&rsquo;s system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards</li><li>
Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines
</li><li>Create and execute validation plans to verify the correctness and performance of calibration firmware and algorithms. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability
</li><li>Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem</li><li>
Develop clear and comprehensive documentation for calibration flows, firmware APIs, and algorithm behavior. Ensure alignment with JEDEC specifications and internal design guidelines
</li><li>Stay updated with emerging DDR technologies and calibration techniques. Propose and implement innovative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces</li></ul><div><b>
PREFERRED EXPERIENCE:</b></div><ul><li>
B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience</li><li>
Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges</li><li>
Circuit timing/STA, and practical experience with tools</li><li>
Working knowledge of C; embedded experience a plus</li><li>
Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards</li><li>
Been exposed to memory controller and PHYs from different IP vendors</li><li>
Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software</li><li>
Version control systems such as Perforce, ICManage or Git</li><li>
Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus</li><li>
Strong verbal and written communication skills</li><li>
Should have experience working in geographically dispersed team and should be a strong team player</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+ yrs of exp</li></ul><p></p><p><br>
#LI-SR4</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

Senior RTL Design Engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
MTS SILICON DESIGN ENGINEER</b></div><div></div><div><b><br>
THE ROLE:</b></div><div>
The focus of this role is to plan, build, and execute the deisgn and validation of new and existing features for AMD&rsquo;s DDR IPs.</div><div></div><div><b><br>
THE PERSON:</b>
</div><div>Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutions&mdash;including RTL logic, firmware routines, and algorithmic flows&mdash;into AMD&rsquo;s system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards</li><li>
Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines
</li><li>Create and execute validation plans to verify the correctness and performance of calibration firmware and algorithms. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability
</li><li>Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem</li><li>
Develop clear and comprehensive documentation for calibration flows, firmware APIs, and algorithm behavior. Ensure alignment with JEDEC specifications and internal design guidelines
</li><li>Stay updated with emerging DDR technologies and calibration techniques. Propose and implement innovative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces</li></ul><div><b>
PREFERRED EXPERIENCE:</b></div><ul><li>
B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience</li><li>
Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges</li><li>
Circuit timing/STA, and practical experience with tools</li><li>
Working knowledge of C; embedded experience a plus</li><li>
Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards</li><li>
Been exposed to memory controller and PHYs from different IP vendors</li><li>
Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software</li><li>
Version control systems such as Perforce, ICManage or Git</li><li>
Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus</li><li>
Strong verbal and written communication skills</li><li>
Should have experience working in geographically dispersed team and should be a strong team player</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+ yrs of exp</li></ul><p></p><p><br>
#LI-SR4</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

Lead RTL Design Engineer with Memory Technologies

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
SE</b><b>NIOR</b><b> SILICON DESIGN ENGINEER</b></div><div></div><div><br>
Locaton: Bangalore</div><div></div><div><b><br>
THE ROLE</b><b>:</b></div><div>
We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.</div><div></div><div><b><br>
THE PERSON:</b></div><div>
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li><div>
Define, develop, and maintain precise DFT-specific timing constraints (scan shift/capture, MBIST, LBIST) ensuring full timing closure without impacting functional timing.</div></li><li><div>
Perform static timing analysis (STA) sign-off on DFT structures (scan chains, BIST controllers, test logic), analyze timing reports, and debug violations.</div></li><li><div>
Validate timing integrity of test clocks, scan enable signals, and control signals across multiple test modes and PVT corners.</div></li><li><div>
Collaborate with design, physical design, and timing teams to resolve test logic timing issues while maintaining overall chip performance.</div></li><li><div>
Ensure DFT timing constraints correctly handle false and multi-cycle paths to avoid timing misinterpretations.</div></li><li><div>
Develop and maintain automation scripts (TCL, Python, Perl) to streamline STA and DV flows, improve efficiency, and generate detailed reports.</div></li><li><div>
Develop and execute comprehensive design verification (DV) plans focused on scan chain insertion, test logic functionality, and robustness.</div></li><li><div>
Create and run verification testbenches for scan chain operations (shift, capture, reset, bypass) and validate DFT features (scan, BIST, compression) via simulation/emulation.</div></li><li><div>
Collaborate with ATPG teams to validate test pattern quality and fault coverage, ensuring high-quality manufacturing test readiness.</div></li><li><div>
Measure and improve test coverage metrics; identify and debug scan-related failures during pre-silicon simulation and support post-silicon debug activities.</div></li><li><div>
Actively contribute to improving DFT timing methodologies and DV verification environments based on silicon feedback and industry best practices.</div></li><li><div>
Work cross-functionally with design, validation, and physical teams to address DV issues and provide feedback to enhance design testability.</div></li><li><div>
Document and report DV plans, timing closure status, verification results, and issues to facilitate clear communication across teams.</div></li><li><div>
Mentor junior engineers on best practices in DFT timing closure and design verification.</div></li></ul><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
Strong hands-on experience in developing and managing timing constraints for scan chains, BIST, and test logic, with expertise in static timing analysis (STA) sign-off using tools like Synopsys PrimeTime or Cadence Tempus.</li><li>
Proven ability to debug and resolve timing violations related to DFT logic, collaborating effectively with design and physical teams to achieve timing closure.</li><li>
Solid background in creating and executing design verification plans for scan chain functionality, BIST, ATPG validation, and compression logic using simulation and verification methodologies.</li><li>
Proficiency in scripting languages (TCL, Python, Perl) for automation of STA and DV flows, test coverage analysis, and regression management.</li><li>
Experience with industry-standard DFT and verification tools such as Synopsys DFT Compiler, Mentor Tessent, and TetraMAX.</li><li>
Familiarity with test pattern generation and validation, ensuring high fault coverage and minimal test patterns.</li><li>
Exposure to multi-mode, multi-corner STA methodologies and test mode timing verification (scan, LBIST, MBIST).</li><li>
Ability to collaborate cross-functionally and contribute to post-silicon debug and silicon bring-up support.</li><li>
Knowledge of advanced node SoC design flows and best practices in DFT timing and DV methodologies</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul><p></p><p><br>
#LI-AA1</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

DFT - Timing

Amazon.com

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><p>
The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.
<br>
<br>
Work hard. Have fun. Make history.
<br>
<br>
We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production.
<br>
<br>
As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability &mdash; from early DFT architecture planning to high-volume silicon bring-up and yield ramp.<br>
<br>
Key job responsibilities<br>
Key job responsibilities<br>
Lead development &amp; implementation of DFT architecture including system level DFT for a full chip<br>
Write and guide others in writing design flow and project documentation.<br>
Own DFT planning, milestone tracking, and cross-functional checklist reviews.<br>
Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists.<br>
Review and sign-off SoC level DFT mode timing closure using static timing analysis<br>
Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon<br>
Keep informed on and introduce new technology into Design-for-Test process as appropriate.</p><h2 class="jobSectionHeader"><b>
BASIC QUALIFICATIONS</b></h2><ul><li>Bachelor's degree in Electrical Engineering or a related field</li><li>15+ years in SoC/ASIC DFT, including 3+ years Leading DFT.</li><li>Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production.</li><li>DFT Architecture Expertise: Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality.</li><li>MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration.</li><li>IEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures.</li><li>DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths.</li><li>RTL and gate-level debug, including mismatch triage and simulation correlation. Insertion and Validation of EFUSE &amp; OTP controllers and related structures during DFT implementation. Tool Proficiency: Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling.</li><li>DFT logic insertion, pattern generation, and diagnostics. Design Background</li><li>Experience in writing verilog/system verilog RTL related to DFT logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets.</li><li>Pattern validation, format conversion, and debugging across wafer sort and final test. Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements.</li><li>Silicon Debug: Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis. Automation Skills:</li><li>Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl. Collaboration: Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing. Execution Excellence: Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success.</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Master's degree or Ph.D. degree in Electrical Engineering or related field</li><li>Leadership: Led multi-site/global DFT teams, mentoring engineers and managing design reviews.</li><li>Drove design-for-test planning in collaboration with customers or design services partners.</li><li>Technical Depth: Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies.</li><li>Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues.</li><li>Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement.</li></ul><br>
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.</div>

Senior DFT Engineer, SSG

Silicon Labs

<div><div>Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world&rsquo;s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at <div>www.silabs.com</div>.</div><div>
Who We Are<br>
Silicon Labs (NASDAQ: SLAB) is a global leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, and robust ecosystem simplify the path to market for customers building smart home, industrial, and commercial IoT products.</div><div>
The Role<br>
We&rsquo;re looking for a Senior Engineer to join our SoC Platform Software team. You&rsquo;ll play a critical role in bringing up new SoCs, developing and maintaining low-level drivers and firmware, and delivering production-quality software functionality across a wide range of embedded platforms.<br>
This role will focus on implementing peripheral drivers, optimizing real-time OS integration, and enabling robust, low-power, high-performance device features used by thousands of developers and millions of devices worldwide.</div><div></div><div>
What You&rsquo;ll Do</div><ul><li>
Develop, maintain, and optimize peripheral drivers (GPIO, UART, I2C/I3C, SPI, DMA, timers, ADC, CAN, SDIO, etc.) in C for multiple SoC families.</li><li>
Lead development and integration of the USB Device stack, including:</li><li>
Control path (EP0), composite/class support (CDC, HID, MSC, DFU, Audio).</li><li>
Transfer management, suspend/resume, LPM/remote wakeup.</li><li>
Protocol compliance and power-aware operation (HS/FS).</li><li>
Integrate and maintain RTOS (e.g., FreeRTOS, Zephyr) for real-time, resource-constrained systems:</li><li>
Task scheduling, ISR design, memory protection (MPU), tickless idle, and synchronization.</li><li>
Support new silicon bring-up: boot sequences, clocking, memory map setup, cache/MPU configuration, and debug interfaces (JTAG/SWD).</li><li>
Contribute to the Gecko SDK: ensuring consistency, quality, and integration with tools like Simplicity Studio.</li><li>
Collaborate with hardware, validation, security, apps, and product teams on feature development, bring-up, and support.</li><li>
Write technical documentation, integration guides, and internal specifications.</li></ul><div>
What You&rsquo;ll Bring</div><ul><li>
BS/MS in Electrical Engineering, Computer Engineering, or related field.</li><li>
7+ years of embedded firmware development experience on ARM Cortex-M/A or RISC-V SoCs.</li><li>
Strong proficiency in C and embedded systems debugging (JTAG, trace analyzers, oscilloscopes).</li><li>
Hands-on experience building and shipping USB Device solutions using vendor or open IP cores (e.g., Synopsys DWC2/3, Cadence, Mentor).</li><li>
Familiarity with USB device class stacks (CDC-ACM, HID, MSC, Audio, DFU).</li><li>
Proven knowledge of RTOS internals and real-time scheduling.</li><li>
Peripheral driver development with DMA and concurrency awareness.</li></ul><div>
Preferred Qualifications:</div><ul><li>
Experience with USB-IF compliance, protocol analyzers (Total Phase, LeCroy, Beagle), or custom descriptors.</li><li>
Familiarity with low-power system design: tickless idle, wake-up sources, retention/sleep modes.</li><li>
Secure firmware development (secure boot, signed updates, debug lockdown) is a plus.</li><li>
Prior experience with Silicon Labs' Gecko SDK and Simplicity Studio toolchain is a strong plus.</li></ul><div><div>
Benefits &amp; Perks:</div></div><div><div>
Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.</div><ul><li>
Equity Rewards (RSUs)</li><li>
Employee Stock Purchase Plan (ESPP)</li><li>
Insurance plans with Outpatient cover</li><li>
National Pension Scheme (NPS)</li><li>
Flexible work policy</li><li>
Childcare support</li></ul></div><div></div><div><i>
Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.</i></div></div>

Senior Engineer – Software Design

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