system validation engineer

Marvell Technology

<div><div>About Marvell</div><div>
Marvell&rsquo;s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.</div><div></div><div>
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.</div><div></div><div>
Your Team, Your Impact</div><div></div>
Marvell&rsquo;s System Validation team within the Data Center Engineering Business Unit contributes to the development, characterization, and Validation of Marvell&rsquo;s next generation Optical Digital Signal Processing (ODSP) products The focus of the team is on optical system platform development and system-level validation in a collaborative, fast-paced environment.<div></div><div>
What You Can Expect</div><div>
As a System Validation Intern, you will:</div><ul><li>
Learn to work independently and methodologically using industry-standard tools.</li><li>
Collaborate with multidisciplinary engineers (system design, hardware, firmware, and validation) to develop characterization and validation tests.</li><li>
Contribute to the design, bring-up and optimization of optical platforms for next-generation ODSP.</li><li>
Perform optical system validation in a supportive and dynamic environment.</li><li>
Develop automatic scripts to support data collection and analysis.</li><li>
Assist with project tasks, reporting, and documentation.</li></ul><div></div><div>
What We're Looking For</div><div>
Minimum Qualifications:</div><div><div><div><div><div><div><div><div><div><ul><li>
Currently pursuing a bachelor&rsquo;s or master&rsquo;s degree in Physics, Electrical Engineering, or other related fields with an anticipated graduation date between Winter 2026 and Spring 2027</li><li>
Strong written and verbal communication skills in English</li><li>
Proficiency with Microsoft Word, Excel, and PowerPoint</li><li>
Effective interpersonal and teamwork skills</li><li>
Proficiency in Python, C, and/or MATLAB</li><li>
Reliable, detail-oriented, and able to work independent</li></ul><div></div><div>
Preferred Qualifications:</div><ul><li>
Knowledge of optics, electrical circuit design, or experiencing reading schematics and layout</li></ul></div></div></div></div></div></div></div></div></div><div></div><div>
Expected Base Pay Range (USD)</div>
31 - 63, $ per hour.<div></div><div>
The successful candidate&rsquo;s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.</div><div></div><div>
Additional Compensation and Benefit Elements</div>
For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness &amp; mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.<div></div><div>
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.</div><div></div><div>
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at <div>TAOps@marvell.com</div>.</div><div></div><div><i>
Interview Integrity</i></div><div><i><br>
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.</i><br>
<br>
<i>Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.</i></div><div></div><div>
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.</div><div></div>
#LI-JY1</div>

System Validation Intern - Master's Degree

<div></div><div><div><div><div><ul><div>2 - 3 Years</div>
<div></div><div>1 Opening</div>
 <div>Hyderabad</div></ul></div><p></p><div><br>
<div><div>
</div></div></div></div><div></div><div><h3 class="jobSectionHeader"><b>Role description</b></h3><br>
<div><div><br>
<b><i>Who we are:</i></b></div>
<div>
At UST, we help the world&rsquo;s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact&mdash;touching billions of lives in the process. Visit us at .</div><br>
<div></div>
<div><b>
The Opportunity</b>:</div>
<div><b>
 Validation Engineer</b></div>
<div></div>
<div><b>Key Responsibilities
</b></div><ul><li> Develop and execute validation plans for USB, audio, display, storage, and power management features. Run standard test suites such as Windows HCK/HLK and internal frameworks (e.g., NVIDIA tools).</li></ul>
<ul><li> Triage issues using tools like Event Viewer, Device Manager, Dmesg, serial/UART logs.</li></ul>
<ul><li> Perform firmware regression testing to ensure backward compatibility and bug verification.</li></ul>
<ul><li> Simulate complex use cases such as device removal during sleep/resume, multi-monitor setups, and hot-plug stress scenarios.</li></ul>
<ul><li> Reproduce failures and isolate issues to the hardware, firmware, or driver layer using structured debug. Log and track bugs using tools such as Jira, Bugzilla, or internal portals. Work closely with BIOS, driver, and hardware engineering teams to analyze and resolve open issues.
</li></ul><ul><li> Contribute to validation coverage reporting, defect dashboards, and triage documentation. Support reproduction and debugging of field/customer-reported issues.</li></ul>
<div><b>
Required Skills:
</b></div><ul><li> Strong knowledge of Windows-based system validation. Experience with firmware, driver, or OS-level debugging. Familiarity with validation tools and test automation environments.
</li></ul><ul><li> Good understanding of platform subsystems: USB, audio, display, storage, power.</li></ul>
<ul><li> Proficiency in defect tracking systems and triage workflows. Excellent communication and cross-team collaboration</li></ul><br>
<div></div>
<div>
 <b>Desired Skills</b>:
</div><ul><li> Bachelor&rsquo;s degree in Computer Engineering, Electrical Engineering, or related field.</li></ul>
<ul><li> 5+ years of experience in platform/system validation, firmware testing, or triage engineering.</li></ul>
<p>
Skills</p>
<ul><li> Windows Os,Debugging,Debugging Tools</li></ul><br>
<div></div>
<div><b><i>
What we believe</i></b><i>:</i></div>
<div><i>
We&rsquo;re proud to embrace the same values that have shaped UST since the beginning. Since day one, we&rsquo;ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.</i></div>
<div><b><i>
Humility:</i></b></div>
<div><i>
We will listen, learn, be empathetic and help selflessly in our interactions with everyone.</i></div>
<div><b><i>
Humanity:</i></b></div>
<div><i>
Through business, we will better the lives of those less fortunate than ourselves.</i></div>
<div><b><i>
Integrity:</i></b></div>
<div><i>
We honour our commitments and act with responsibility in all our relationships.</i></div><br>
<div></div>
<div><b><i>
Equal Employment Opportunity Statement</i></b></div><br>
<div></div>
<div><i>
UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.</i></div><br>
<div></div>
<div><i>
All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.</i></div><div><br>
<i>
UST</i><i> reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.</i></div><br>
<div></div>
<ul><li><i>To support and promote the values of UST.</i></li></ul>
<ul><li><i>Comply with all Company policies and procedures</i></li></ul></div>
<h3 class="jobSectionHeader"><b>Skills</b></h3>
<div><p>Windows Os,Debugging,Debugging Tools</p></div></div></div></div><p></p>
<br><div><h3 class="jobSectionHeader"><b>About UST</b></h3>
<div>UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world&rsquo;s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients&rsquo; organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact&mdash;touching billions of lives in the process.</div></div>

Validation Engineer

<div></div><div><div><div><div><ul><div>1 Opening</div>
 <div>Redmond</div></ul></div><p></p><div><br>
<div><div>
</div></div></div></div><div></div><div><h3 class="jobSectionHeader"><b>Role description</b></h3>
<div><p><b>Surface Validation Engineer</b></p>
<p><b>
Associate II - Semiconductor Product Validation</b></p><br>
<p></p>
<p><b>
Who We Are:</b></p>
<p>
Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do. We help them create transformative experiences and human-centered solutions for a better world.</p>
<p>
UST is a mission-driven group of 29,000+ practical problem solvers and creative thinkers in more than 30 countries. Our entrepreneurial teams are empowered to innovate, act nimbly, and create a lasting and sustainable impact for our clients, their customers, and the communities in which we live.</p>
<p>
With us, you&rsquo;ll create a boundless impact that transforms your career&mdash;and the lives of people across the world.</p>
<p>
Visit us at UST.com.</p><br>
<p></p>
<p><b>
You Are:</b></p>
<p>
UST is seeking an experienced <b>Surface Validation Engineer</b> to lead validation efforts across next-generation Windows device platforms. The ideal candidate will have deep technical expertise in system-level validation, hardware-software integration, and platform bring-up. You will play a key role in ensuring product quality, performance, and reliability across client and commercial device lines.</p><br>
<p></p>
<p><b>
The Opportunity:</b>
</p><ul><li> Own end-to-end validation of Windows hardware platforms including SoC, BIOS, firmware, drivers, and OS integration.
</li></ul><ul><li> Develop, execute, and automate comprehensive test plans for platform, subsystem, and feature validation (CPU, memory, storage, graphics, I/O, sensors, connectivity, etc.).
</li></ul><ul><li> Collaborate with cross-functional teams including Silicon, Firmware, BIOS, Driver, and OS teams to triage, debug, and root-cause complex system-level issues.
</li></ul><ul><li> Drive validation readiness from prototype bring-up through production release.
</li></ul><ul><li> Utilize telemetry, logs, and trace data to perform issue isolation and failure analysis.
</li></ul><ul><li> Develop Python- or PowerShell-based automation tools to enhance validation &amp; debug coverage and efficiency.
</li></ul><ul><li> Conduct performance, power, thermal, and reliability validation in pre-production environments.
</li></ul><ul><li> Provide technical reports, dashboards, and sign-off criteria for product readiness.
</li></ul><ul><li> Interface with ODM/OEM partners and component vendors to align validation strategies and ensure platform quality metrics are met.
</li></ul><ul><li> File, triage, and follow through on bugs using tracking tools like Azure DevOps, Jira, or internal portals
</li></ul><ul><li> Work closely with cross-functional teams to replicate issues and ensure test coverage
</li></ul><ul><li> Assist with testbed bring-up and sanity testing for new hardware platforms
</li></ul><ul><li> Participate in daily syncs and report test execution status clearly.</li></ul><br>
<p></p>
<p>
This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.</p><br>
<p></p>
<p><b>
What You </b><b>Need:</b></p>
<ul><li> <b>Qualification:
</b></li></ul><div>o Bachelor&rsquo;s or Master&rsquo;s degree in Computer Engineering, or related field OR 5+ years of hands-on experience in system/platform validation, preferably on Windows-based devices.</div><br>
<div></div>
<ul><li> <b>Required Skills:
</b></li></ul><div>o Strong understanding of PC architecture, SoC subsystems, BIOS/UEFI, ACPI, and Windows driver model.
</div><div>o Proficiency in debugging tools (WinDbg, logic analyzer, power analyzer, trace tools, etc.).
</div><div>o Experience in system bring-up, firmware validation, and hardware/software integration.
</div><div>o Scripting or automation experience in Python, PowerShell, or C#.
</div><div>o Excellent analytical, problem-solving, and cross-team communication skills.</div><br>
<div>
</div><ul><li> <b>Desired Skills:
</b></li></ul><div>o Experience validating Windows, OEM, or other client compute platforms (Intel, AMD, or ARM-based).
</div><div>o Familiarity with Windows HLK, WHQL, and Microsoft certification workflows.
</div><div>o Experience with validation infrastructure, CI/CD automation frameworks, or test management tools (JIRA, TestRail, Azure DevOps).
</div><div>o Knowledge of system power/performance optimization techniques.
</div><div>o Proven ability to lead validation strategy and mentor junior engineers.</div><br>
<p></p>
<p>
Compensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.</p>
<p><b>
Role Location:</b> <b>Washington</b></p>
<p><b>
Compensation Range</b>: $56,000-$84,000</p><br>
<p></p>
<p><b>
Benefits</b></p>
<p>
Full-time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company&rsquo;s 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company-paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short- and long-term disability benefits. Regular employees may purchase additional voluntary short-term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines. Benefits offerings vary in Puerto Rico.</p>
<p>
Part-time employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company&rsquo;s 401(k) Retirement Plan with employer matching.</p>
<p>
Full-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company&rsquo;s 401(k) program with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance.</p>
<p>
Part-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year).</p>
<p>
All US employees who work in a state or locality with more generous paid sick leave benefits than specified here will receive the benefit of those sick leave laws.</p><br>
<p></p>
<p><b>
What we believe:</b></p>
<p>
We proudly embrace the values that have shaped UST since day one. We build our culture of Humility, Humanity, and Integrity. These values inspire us to nurture a people-first, human centric culture that fosters diversity, prioritizes sustainable solutions, and keeps our people and clients at the forefront of all decisions.</p>
<p><b>
Humility:</b></p>
<p>
We will listen, learn, be empathetic and help selflessly in our interactions with everyone.</p>
<p><b>
Humanity:</b></p>
<p>
Through business, we will better the lives of those less fortunate than ourselves.</p>
<p><b>
Integrity:</b></p>
<p>
We honor our commitments and act with responsibility in all our relationships.</p>
<p><b>
Equal Employment Opportunity Statement</b></p><div><br>
UST is an Equal Opportunity Employer.</div><br>
<div></div>
<p>
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. We will consider qualified applicants with arrest or conviction records in accordance with state and local laws and &ldquo;fair chance&rdquo; ordinances.</p>
<div>
UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.</div><br>
<div></div>
<div>
</div><div>#UST</div></div>
<h3 class="jobSectionHeader"><b>Skills</b></h3>
<div><p>Windows Platform Validation,BIOS/FW,WHQL/WHCK</p></div>
<h3 class="jobSectionHeader"><b>Benefits</b></h3>
<h3 class="jobSectionHeader"><p><b>Compensation range: $ 56,000.00 to 84,000.00 per year</b></p></h3></div></div></div><p></p>
<br><div><h3 class="jobSectionHeader"><b>About UST</b></h3>
<div>UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world&rsquo;s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients&rsquo; organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact&mdash;touching billions of lives in the process.</div></div>

Surface Validation Engineer

Capgemini Engineering

<div><div><div><div><h2 class="jobSectionHeader"><b>Job Description
</b></h2></div><div><p><b>Choosing Capgemini means choosing a place where you&rsquo;ll be empowered to shape your career, supported by a collaborative global community, and inspired to reimagine what&rsquo;s possible. Join us in helping leading Consumer Products and Retail Services (CPRS) organizations unlock the value of technology and drive scalable, sustainable growth.
</b></p><p><b>Your Role
</b></p><p><b>As a System Software Verification Engineer, you will be responsible for validating embedded software components across pre-silicon and post-silicon platforms. You will work on board bring-up, driver validation, and system-level testing for ARM-based platforms, ensuring robust and reliable software delivery. Your role will involve close collaboration with development teams to analyze failures, automate test cases, and maintain test frameworks for continuous integration and verification.
</b></p><p><b>In this role, you will:
</b></p><ul><li><b>Perform board bring-up activities for software components such as bootloaders, platform managers, Linux Kernel, Linux drivers, Baremetal drivers, and applications on ARM-based boards.
</b></li><li><b>Conduct testing and verification of Linux Kernel and drivers including I2C, Flash, USB, Ethernet, PCIe, and DDR memory.
</b></li><li><b>Develop and execute test plans to evaluate firmware functionality, security, and efficiency using emulation and evaluation boards.
</b></li><li><b>Analyze, debug, and track test failures; collaborate with development teams to resolve issues.
</b></li><li><b>Run regression tests, triage issues, log defects, and follow up on closure.
</b></li><li><b>Automate functional and system-level tests using Python and integrate them into the test automation framework.
</b></li><li><b>Maintain and update test artifacts in line with evolving test cases and frameworks.
</b></li></ul><p><b>Your Profile
</b></p><ul><li><b>B.E/B.Tech or M.E/M.Tech in Electronics &amp; Communications or Computer Science.
</b></li><li><b>Hands-on experience in verification and testing of Linux-based embedded systems.
</b></li><li><b>Proficient in Linux device driver validation on Linux, Baremetal, and RTOS platforms.
</b></li><li><b>Skilled in compiling, cross-compiling, debugging, and deploying Bootloader, TF-A, Linux Kernel, Device Tree, Middleware, and Baremetal applications using JTAG debuggers and emulators.
</b></li><li><b>Strong understanding of SoC/processing technologies such as ARM, RISC-V, or x86, including MMU, interrupt handling, and cache management.
</b></li><li><b>Experience with peripheral interfaces like UART, I2C, SPI, USB, SD, eMMC, QSPI, and PCIe.
</b></li><li><b>Capable of defining, designing, and developing manual and automated test cases for embedded systems.
</b></li><li><b>Programming skills in C/C++, Makefile, linker scripts, and scripting languages like Python, Shell, or Tcl.
</b></li><li><b>Familiarity with version control and CI/CD tools such as GIT, Jenkins, Pytest.
</b></li><li><b>Exposure to tools like VIVADO, VITIS, and configuration management platforms like JIRA and Confluence is a plus.
</b></li></ul><p><b>What You&rsquo;ll Love About Working Here
</b></p><p><b>We value flexibility and support our employees with remote work options and adaptable schedules to maintain a healthy work-life balance. Our inclusive culture brings together diverse professionals committed to growth, innovation, and excellence. You&rsquo;ll have access to continuous learning opportunities and certifications in emerging technologies like cloud and AI.
</b></p><p><b>About Us
</b></p><p><b>At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world&rsquo;s most innovative companies unleash their potential.</b></p></div></div></div></div>

System Software Verification Engineer

Synaxis Informatic Tech Solutions

<p>Seeking an experienced Senior Validation Engineer to ensure performance, reliability, and compliance of advanced energy metering solutions based on DLMS protocols for our esteemed client. This role focuses on validation activities for smart metering devices, network communication, and cyber security in the energy sector.</p><p>Required Skills &amp; Qualifications<br/>*Deep working knowledge of Gurux DLMS, DLMS/COSEM (IEC 62056) standards, and smart metering communication protocols.<br/>*Experience with validation tools: Optical Probe, RS-485, RF, GSM/4G/NB-IoT connectivity modules.<br/>*Proficiency in Python for test automation, data analysis, and reporting.<br/>*Understanding of cyber security concepts as applied to energy metering and IoT devices.<br/>*Analytical thinking, documentation skills, and collaborative mindset essential.<br/>*Bachelor&rsquo;s in Electronics, Electrical, Computer Engineering, or related field.</p><p>Job Type: Full-time</p><p>Pay: &#8377;800,000.00 - &#8377;1,000,000.00 per year</p><p>Application Question(s):</p><ul><li>Available for F2F after initial Virtual Interview..?</li></ul><p>Experience:</p><ul><li>Gurux DLMS, DLMS/ COSEM (IEC 62056) protocol: 5 years (Required)</li><li>Functional testing: 3 years (Required)</li><li>AMI Head-End Systems, MDM, and field meter integration.: 2 years (Preferred)</li></ul><p>Location:</p><ul><li>Hyderabad, Telangana (Required)</li></ul><p>Work Location: In person</p>

Sr. Validation Engineer – DLMS

<div><div>About Marvell</div><div>
Marvell&rsquo;s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.</div><div></div><div>
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.</div><div></div><div>
Your Team, Your Impact</div><div></div>
The Post-Silicon Validation team is instrumental in designing test platforms and executing comprehensive validation processes that span functional, electrical, and system-level testing, along with firmware and software validation. The team also supports the integration of Marvell solutions into customer platforms, including Ethernet switches and Wi-Fi access points.<br>
<br>
System Validation Engineers ensure Marvell&rsquo;s connectivity products meet rigorous performance and reliability standards across enterprise, industrial, and cloud data center deployments.<div></div><div>
What You Can Expect</div><ul><li>
Own responsibility for Marvell Ethernet Cu PHY Validation in post-silicon environment.</li><li>
Develop System-level and Silicon-level test plan for Marvell Alaska-M Ethernet PHY and Alaska-C HSC Retimer PHY products.</li><li>
Define, document, execute and report the overall PHY validation/test plan for Marvell storage devices.</li><li>
Lab-based silicon bring-up and unit test execution focused on 10BASE-T Physical and PCS layer hardware and firmware functionality.</li><li>
Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.</li><li>
Analyze and debug issues on PHY protocol of storage interface (SERDES, Ethernet).</li><li>
Troubleshoot failing tests using diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers.</li><li>
Lead collaborative technical discussions to drive resolution on technical issues. Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to Cu PHY and High Speed SERDES Retimer PHY.</li><li>
Work closely with customers to address design issue and debug failure cases.</li></ul><div></div><div>
What We're Looking For</div><div>
As a Principal Engineer in Hardware and Silicon Validation at Marvell, you will play a key role in the development and delivery of Marvell&rsquo;s Alaska-M and Alaska-C Ethernet PHY products. Your responsibilities will include validating high-performance networking hardware, such as copper 10GBASE-T Ethernet PHYs and high-speed PAM4 SERDES retimer transceivers&mdash;critical technologies that enable high-density Ethernet switch applications across enterprise, PoE, wireless, and data center environments.</div><div></div><ul><li>
Bachelor&rsquo;s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master&rsquo;s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.</li><li>
Strong understanding of high-speed SERDES, equalization technique and Ethernet Networking protocols.</li><li>
5+ years of experience with High Speed IO testing, Analog AFE characterization debugging and validation</li><li>
Strong lab skills with hands on experience, in system bring up, system testing and debug.</li><li>
In-depth working knowledge of test equipment used for PAM4 SERDES characterization and 10GBASE-T Cu PHY Ethernet AFE Analog ADC, DAC characterization (Scope, BERT, Network analyzer, Spectrum Analyser etc.).</li><li>
Strong analytical, problem-solving and communication skills.</li></ul><div></div><div>
Preferred:</div><ul><li>
Working knowledge of Ethernet Networking interface and characterization.</li><li>
Working knowledge and experience on Ethernet and PAM4 SERDES is a definite plus.</li><li>
Extensive knowledge of the physical and protocol levels (PMA, PCS, MAC) of one or more common high-speed interfaces is an asset.</li><li>
Working knowledge of hardware board design; able to read board schematics and board layout.</li><li>
Working experience with Python.</li></ul><div></div><div>
Expected Base Pay Range (USD)</div>
144,800 - 214,340, $ per annum<div></div><div>
The successful candidate&rsquo;s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.</div><div></div><div>
Additional Compensation and Benefit Elements</div>
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.<div></div><div>
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.</div><div></div><div>
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at <div>TAOps@marvell.com</div>.</div><div></div><div><i>
Interview Integrity</i></div><div><i><br>
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.</i><br>
<br>
<i>Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.</i></div><div></div><div>
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.</div><div></div>
#LI-NF1</div>

Principal Engineer, Hardware Systems & Silicon Validation

Mercedes-Benz Group

<div><div><div><div><div><div><div><div>T&auml;tigkeitsbereich:Forschung &amp; Entwicklung incl. Design</div></div><div><div>
Fachabteilung:Body &amp; Comfort, PNM, Body EE Integration</div></div><div><div>
Gesellschaft:Mercedes-Benz Research and Development India Private Limited</div></div><div><div>
Standort:Mercedes-Benz Research and Development India Private Limited, Bangalore</div></div><div><div>
Startdatum:01.01.2026</div></div><div><div>
Ver&ouml;ffentlichungsdatum:10.11.2025</div></div><div><div>
Stellennummer:MER0003TKA</div></div><div><div>
Arbeitszeit:Vollzeit</div></div></div></div><div><div><div>
</div></div></div></div></div></div><div><div><div><div>Aufgaben<div><div><p>
Senior Program Manager, Body &amp; Comfort HiL Testing</p><p>
Mercedes-Benz Research and Development, India is seeking a project manager with a strong technical background in HiL testing for .</p><p></p><p><br>
Key Job Responsibilities:</p><ul><li>
Responsible to lead HiL testing project end-to-end along the automotive V-cycle</li><li>
Creation and updating the test specification, scripting for components, systems, integration of safety requirements;</li><li>
Responsible for ensuring Product Delivery as per the specified requirements, timelines and cost.</li><li>
Coordination of test activities / clarifications with Mercedes-Benz Germany for the component and system requirements clarification</li><li>
Accountable for effort estimations and work breakdown.</li><li>
Responsible for implementing Project Management practices to comply with the V-model for development.</li><li>
Responsible for mentoring and overseeing the activities of the HiL testing team with an aim to improve the overall Product Understanding.</li></ul><p></p><p><br>
Basic Qualification:</p><ul><li>Bachelors or Master&rsquo;s Degree in Computer Science/Electrical &amp; Electronics/ Masters in Computer Applications</li><li>12-15 years of overall experience in automotive HiL Validation activities including project management, requirements engineering, system analysis.</li><li>
Good understanding of Body &amp; Comfort systems and components.</li><li>Must have played a key role in the complete product validation of at least 4 - 5 Products.</li><li>
Good exposure to configuration management tools like PVCS, SVN, GIT and requirement management tool, DOORS, CAN and FLEXRAY protocol knowledge and ISO 26262 is preferred.</li></ul></div></div></div></div></div><div><div><div>
Qualifikationen<div><div><ul><li>Good communication skills and ability to work in &amp; contribute as a good team player</li><li>Experience in the automotive field and exposure of multi-cultural environment is an added advantage.</li><li>Vehicle driving skills</li><li>Basic knowledge on German language preferred.</li></ul></div></div></div></div></div></div><div><div><div>
Benefits</div><div></div><div><div><div>
Mitarbeiterrabatte m&ouml;glich</div><div></div><div>
Gesundheitsma&szlig;nahmen</div><div></div><div>
Mitarbeiterhandy m&ouml;glich</div><div></div><div>
Essenszulagen</div><div></div><div>
Betriebliche Altersversorgung</div><div></div><div>
Hybrides Arbeiten m&ouml;glich</div><div></div><div>
Mobilit&auml;tsangebote</div><div></div><div>
Mitarbeiter Events</div><div></div><div>
Coaching</div><div></div><div>
Flexible Arbeitszeit m&ouml;glich</div><div></div><div>
Kinderbetreuung</div><div></div><div>
Parkplatz</div><div></div><div>
Kantine, Caf&eacute;</div><div></div><div>
Gute Anbindung</div><div></div><div>
Barrierefreiheit</div><div></div><div>
Betriebsarzt</div></div></div></div></div><div></div><div><div><div>
KontaktMercedes-Benz Research and Development India Private Limited<div><div>
Plot No. 5-P, EPIP 1st Phase560066 BangaloreDetails zum Standort</div><div>
Jacob Cyril E-Mail: jacob.cyril@mercedes-benz.com</div></div></div></div></div></div><div></div>

Sr Program Manager - VANs Body & Comfort Validation

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