Senior Design Engineer

OUR STORY

At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.

When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.

Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.

Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

Roles : SoC RTL Designer

Job Description :

SoC design engineer with extensive experience and proven track record in SoC/full-chip micro architecture and design with solid focus on delivering the products across various tech nodes. Individual should have very good hold on SoC global specs and functionalities like core, platforms, clock, reset & power, etc. Must have good understanding on adjoining SoC implementation functions like functional verification, DFT, physical implementation, timing analysis, pre & post-Si validation, test and product engineering etc.

The SoC RTL design engineer will be closely working and collaborating with systems teams and driving RTL design teams for specification development of IP’s, complex subsystems, and chip-top - taking the design from spec definition to RTL development and integration, through entire RTL2GDS flow.

Responsibilities include but not limited to:

Drive architecture & application teams in converging to an optimal specification from performance, design effort/cost point of view. This includes detailed technical discussions and evaluations on IP choices and specifications, SoC architecture definitions covering different core and memory subsystems, solutions for clocking, power management, interconnect etc with target of PPA optimization to grant a competitive balance between product features and time-to-market.

Close engagement with systems teams and customer interfaces to enable correct design decisions while working to build and develop system level knowledge within the design team.

Conducts analyses covering feasibility studies, risk analysis, power, die size estimation etc.

Drive design implementation functions including sub-groups for RTL development and top integration, verification, performance evaluation and pre-Si validation, DFT, physical implementation team for execution of entire RTL2GDS flow.

Running frequent reviews of the corresponding design ownership across development functions, closely monitoring and tracking, and provide technical leadership to individuals from outside the function and owning the outcome of the design developed

Collaborates with the teams across project core team members like engineering, validation, packaging, quality & reliability, marketing etc.

Technical skills/background:

Qualification: Bachelors/Masters in Electronics/Electrical Engineering

Experienced about system applications on aspects related to architectural choices in order to optimize for device performance, power and area.

Good knowledge and understanding of advanced ARM real time and application CPU cores and memory subsystems, system bus architectures (like AHB/AXI), Arteris NOC and other interconnect technologies, debug subsystems, critical aspects like SoC clocking, reset and power mgmt., high speed SerDes, analog integration, RTL design and SoC integration with multiple asynchronous clock domains, bottlenecks identification, timing issues anticipation and resolution.

Competent on power and clocking architectural concepts, capable of driving their definitions and anticipate potential implementation issues for high frequency designs.

Design experience in mid-high complexity product developments in FDSOI 28nm, 16 FFC, 7nm technology nodes.

Knowledge of Automotive Functional Safety ISO26262 is a big plus.

Leadership Skills:

Good negotiator and able to manage tough situations.

Adaptability to align and balance priorities vs timelines

Should possess strong communication skills to ensure effective interaction both with Management and internal project/design sub-groups members

Good interpersonal skills.

Provide direction, mentoring, and leadership to small to medium-sized technical groups.

ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.

To discover more, visit st.com/careers.