Senior DFT Engineer

Greeting from Swedium Global Services.

We have an immediate opportunity for Senior DFT Engineer.

JD :

Experience-7+ Years

Expected Start date: ASAP

Location- Onsite in Bangalore -5 Days of office

Job Name: DFT Engineer-ASIC

Job Summary

We are seeking a DFT Engineer to join our ASIC design team to develop and implement design-for-test methodologies for complex SoCs. The DFT engineer will be responsible for scan insertion, BIST implementation, ATPG pattern generation, and test coverage analysis to ensure high-quality, testable silicon.

Key Responsibilities

• Develop and implement DFT architecture for ASIC/SoC designs in collaboration with front-end and back-end design teams.
• Insert and verify scan chains, boundary scan (JTAG), MBIST, and LBIST structures at RTL or gate level.
• Perform ATPG pattern generation for stuck-at, transition, and path delay faults; analyze and improve test coverage.
• Plan and integrate test compression and diagnostic features to reduce test time and cost.
• Ensure DFT rule compliance throughout the synthesis and implementation flow.
• Collaborate with the physical design team for DFT constraint setup, timing closure, and test mode verification.
• Support silicon bring-up, pattern validation, and failure debug during post-silicon testing.
• Maintain DFT scripts and automation for improved efficiency and consistency across projects.
• Work with ATE (Automated Test Equipment) engineers to ensure smooth pattern transfer and test execution.
• Document DFT methodologies, coverage metrics, and sign-off reports.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
• 7+ years of hands-on experience in ASIC/SoC DFT implementation.
• Strong understanding of:
• Scan insertion and scan architecture
• ATPG (stuck-at, transition faults)
• MBIST/LBIST methodologies
• Boundary scan (IEEE 1149.1)
• Proficiency in DFT EDA tools, such as:
• Synopsys DFT Compiler, TetraMAX / TestMAX
• Siemens (Mentor) Tessent
• Cadence Modus
• Solid understanding of ASIC design flow — synthesis, timing, verification, and P&R.
• Working knowledge of Verilog/SystemVerilog and scripting languages (TCL, Perl, Python, or Shell).
• Familiarity with ATE testing concepts and pattern debug.
• Excellent problem-solving, analytical, and communication skills.

If anyone interested in this assignment, kindly reach out to akshatha.mogerti@swediumglobal.com & 8197100437.

Job Types: Full-time, Permanent

Pay: Up to ₹3,500,000.00 per year

Benefits:

• Cell phone reimbursement
• Health insurance
• Provident Fund

Work Location: In person