Senior STA Engineer (SI50FF RM 3702)

Position: Senior STA Engineer (SI50FF RM 3702)

JD/Expectations : –

Timing analysis, validation and debug across multiple PVT conditions using Tempus.

Familiar with Tempus DMMMC flow for STA and logical/physical aware ECO flows focusing timing and leakage optimization.

Peripheral timing checks.

STA setup, convergence, reviews and signoff for multi-mode (func/scan/atspeed/atspeed exceptions), multi-voltage domain designs.

Review of Unconstrained endpoints and check timing reports.

Proficient in STA and timing methodologies with good understanding of noise, crosstalk, and OCV effects.

Should have worked on both block level and full chip timing closure in 16nm, 5nm and below.

Additionally, closely interact with designers/synthesis/PNR team to provide the feedback to ensure smooth timing closure.

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