STA Engineer

Job Description:
We are seeking an experienced Static Timing Analysis (STA) Engineer to join our team. The ideal candidate will have strong expertise in STA setup, timing convergence, and sign-off processes across complex, multi-mode, multi-voltage domain designs. The role requires deep understanding of STA methodologies, timing validation, and cross-functional collaboration with physical design and layout teams.

Location: Bangalore
Experience: 5 to 8 Years

Responsibilities:

• Perform STA setup, convergence, reviews, and sign-off for multi-mode, multi-voltage domain SoC designs.
• Conduct timing analysis, validation, and debug across multiple PVT (Process, Voltage, Temperature) corners using Cadence Tempus or Synopsys PrimeTime at the full-chip level.
• Execute STA flow optimization and ensure Spice-to-STA correlation for improved accuracy and efficiency.
• Collaborate with physical design, RTL, and layout teams to ensure robust timing closure and design quality.
• Perform detailed analysis of cross-talk noise, signal integrity, and layout parasitic extraction (LPE) impacts on timing.
• Handle feedthrough timing paths and ensure proper constraint management.
• Generate timing reports, identify violations, and propose effective solutions for closure.

Required Skills & Expertise:

• Strong hands-on experience with STA tools such as Cadence Tempus (mandatory) or Synopsys PrimeTime.
• Proven experience in timing sign-off for multi-mode and multi-corner designs.
• Sound knowledge of signal integrity, cross-talk, noise analysis, and layout parasitic extraction concepts.
• Experience in debugging complex timing issues and driving them to closure.
• Good understanding of SoC design flow from synthesis to sign-off.
• Excellent analytical, problem-solving, and communication skills.