Technical Intern, CAD Flow

Description

Invent the future with us.

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team - we’d love to have you apply!

About the role:

As part of the CAD team, own and implement large partitions of high-performance processor blocks using digital design implementation tools.

The Ampere Internship program focuses on you to build your networks, support your efforts in making an impact, and giving you exposure to what Ampere does and how Ampere operates across the company. We want you to leave with the feeling that what you've worked on made a difference, a new level of confidence of what you're capable of, technical expertise, and a new network of contacts.

Internship period is full-time for summer 2026 (May/June - August/September) in Santa Clara, CA.

What you’ll achieve:

• Design, and implement solutions using knowledge of timing, floor-planning, high speed design techniques, and formal verification techniques
• Apply semi-custom, and ASIC-methodologies, as required, to run, synthesis, placement, CTS, routing, and complete other physical design tasks to make the block ready for sign-off
• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality
• Implement lower-geometry designs using CMOS-7nm rules, device characteristics to implement data-paths, and large physical blocks
• Use state-of-the-art macro-compilers, design-cell libraries to provide appropriate design libraries to the processor design team

About you:

• Hands on experience in floor planning, place & route, power and clock distribution, pin placement and timing constraints generation
• Timing convergence using high speed design techniques
• Physical design of high frequency chips with emphasis on successful timing closure
• Excellent understanding of geometry/ process/ device technology implications on physical design. 16nm and 7nm experience is required
• Good understanding of static timing analysis (STA), EM/IR and sign-off flow Experience in physical design verification
• Good programming/scripting skills: Tcl, python, expect, shell
• Experience or coursework in AI and machine learning (ML)

Education:
Currently pursuing a master’s degree in Electrical Engineering, specialization: VLSI design, high-speed microprocessor design

What we’ll offer:
At Ampere we believe in taking care of our interns and providing a competitive rewards package that includes an hourly rate and comprehensive benefits. The pay range for this role is between $52 and $57 per hour.

Benefits highlights include:

• Premium medical, dental, and vision insurance
• Mentorship and on-the-job training from industry experts
• Ergo friendly desk set-up
• Vibrant game rooms to take a break and bond with colleagues
• Micro-kitchens with a variety of healthy snacks, espresso, and refreshing drinks

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our interns to do more and grow more. We are excited to share more about our internship opportunities with you through the interview process.

Internships are open to all eligible students regardless of age including veterans who returned to school.

#LI-TC

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.