ASIC Architect

Employment Type: Full-Time

About Us

Datavault AI, along with its event-technology subsidiary Event Citadel (formerly CompuSystems), operates across a diverse portfolio of technology and service divisions.

Datavault AI Inc. delivers high-performance computing software, Web 3.0 data-management solutions, and advanced audio technologies to a broad range of industries. Its Acoustic Science division licenses spatial and multichannel HD audio technologies—including ADIO®, WiSA®, and Sumerian®—to customers in sports & entertainment, events & venues, automotive, finance, and other sectors.

Event Citadel (formerly CompuSystems), founded in 1976, is a trusted provider of end-to-end event technology solutions, offering registration, ticketing, lead retrieval, and attendee-engagement services for events of all sizes across trade, association, corporate, and government markets.

Job Description

The ASIC Architect design defines, and optimizes high-performance, power-efficient, and cost-effective semiconductor chip architectures, translating product requirements into technical specifications for development teams. They model system behavior, define microarchitecture, and lead cross-functional efforts involving IP integration, verification, and physical design.

The Datavault Acoustics Division, WiSA Technologies, is working to develop our third-generation technology. WiSA HT was a custom ASIC, WiSA E is designed to work with off the shelf IoT devices, like ESP32. Our Third-Generation technology will be an ASIC, that leverages off the shelf Intellectual Property (SoC Design, Radio, WiFi, etc.) to for a device that can work with both WiSA HT and WiSA E.

A successful candidate must understand how to balance cost and performance to reach our target customer segment of high performance and high volume. WiSA HT has the best specifications on the market for Wireless Audio, 5ms Latency and sub 21uS speaker to speaker synchronization while WiSA E has 20ms Latency and sub21uS synch. This product will meet both specs depending on the specific mode we operate.

Key Responsibilities

• Architecture Definition: Create chip-level and subsystem specifications, including memory hierarchy, high-speed interfaces, and data paths.
• IP Vendor Management: Partner with an IP Vendor to speed the development of our ASIC.
• Modeling & Simulation: Develop performance models and simulators to evaluate workloads and optimize Power, Performance, Area, and Cost (PPAC).
• Specification Development: Author detailed technical documents outlining microarchitecture and design constraints.
• Cross-Functional Leadership: Collaborate with RTL designers, verification, and software teams to ensure feasibility and guide implementation.
• Trade-off Analysis: Analyze and decide on design trade-offs to balance performance with power and area constraints.
• Technical Guidance: Mentor junior engineers and promote best practices in design and verification.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related fields.
• Significant experience (often 6+ years) in silicon architecture, performance modeling, or design.
• Strong skills in C++, Python, System Verilog, and architectural modeling tools.
• Deep understanding of computer architecture, AI/ML accelerator design, or GPU architecture.
• Excellent communication for documenting specs and negotiating technical tradeoffs.

What We Offer

• Competitive salary and benefits package.
• A fast-paced, high-impact work environment.
• Opportunity to work closely with executive leadership.
• The chance to work with cutting-edge technologies and make a significant impact.
• A culture of innovation, ownership, and growth.