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AMD is seeking a Senior Analog Layout Engineer with 5+ years of hands-on experience in TSMC 2nm/3nm advanced nodes. The role involves custom analog/mixed-signal layout development for high performance CPU/GPU/SoC designs, ensuring DRC/LVS/ERC/EM IR clean layouts. The candidate should have strong expertise in FinFET technologies, analog layout fundamentals (matching, parasitics, noise), and proficiency with Cadence Virtuoso, with close collaboration across design and foundry teams.
vlsi design,analog layout,tsmc 2nm/3nm,cpu/gpu/soc design,
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