Org Linked

Role: DFT EngineerExperience: 5+ yearsContract Duration: 6 Months (EXTENDABLE)Work Location: Bangalore (Onsite)Client: ARMJob Description:<ul><li>Strong experience with DFT tools &amp; flow (Mentor Tessent)</li><li>Hands-on RTL-level DFT implementation</li><li>LEC at RTL&#8239;level (pre-DFT vs post-DFT) and gate level</li><li>Experience at SoC and Subsystem/Block/Partition level</li><li>SSN experience is a must</li><li>Scan, MBIST, OCC, EDT&#8239;insertion using ARM DFT flow</li><li>Pattern generation, retargeting &amp; simulation at block and SoC level</li><li>Zero delay/timing simulation using SDF</li><li>Coverage closure experience</li><li>Scan synthesis and timing constraints creation</li></ul>Job Types: Full-time, PermanentWork Location: In person

6 Months contract with possibility of extension

Collaborating with a world-class engineering team at ARM in Bangalore, you'll implement advanced DFT solutions using Mentor Tessent to enhance silicon testability across SoCs and subsystems. From RTL-level design changes to scan, MBIST, OCC insertion and coverage closure, your expertise ensures high-quality chips ready for mass production.

DFT Engineer -Mentor Tessent

DFT tools

Mentor Tessent

RTL-level DFT implementation

LEC at RTL and gate level

SoC and Subsystem/Block/Partition level DFT

Scan insertion

MBIST

EDT insertion

Pattern generation

Retargeting

Simulation at block and SoC level

Zero delay/timing simulation

Coverage closure

Scan synthesis

Timing constraints creation

JTAG

Boundary Scan

Fault Simulation

DFT Verification Tools

Scripting (TCL, Perl)

Join Org Linked and explore exciting career opportunities. They're hiring for various roles with options for remote or on-site work. Apply today and become part of their innovative team.

Org Linked hiring DFT Engineer -Mentor Tessent in near you

DFT Engineer -Mentor Tessent

Maintenance head / Sr. Engineer

Maintenance Head