Formal Verification Engineer

Project Role : Formal Verification Engineer
Project Role Description : Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.
Must have skills : SoC Verification
Good to have skills : NA
Minimum 5 year(s) of experience is required
Educational Qualification : 15 years full time education

Summary: As a Formal Verification Engineer, you will ensure design correctness using mathematical methods such as model checking and equivalence checking. Your typical day will involve analyzing design specifications, developing formal models, and applying verification techniques to detect corner-case bugs early in the design cycle. This proactive approach will significantly enhance the quality of the designs and reduce the overall verification time, allowing for a more efficient development process. Roles & Responsibilities: - Expected to be an SME. - Collaborate and manage the team to perform. - Responsible for team decisions. - Engage with multiple teams and contribute on key decisions. - Provide solutions to problems for their immediate team and across multiple teams. - Mentor junior team members to enhance their skills and knowledge in formal verification. Professional & Technical Skills: - Must To Have Skills: Proficiency in SoC Verification. - Strong understanding of formal verification techniques and methodologies. - Experience with model checking and equivalence checking tools. - Familiarity with hardware description languages such as Verilog or VHDL. - Ability to analyze complex design specifications and identify potential issues. Additional Information: - The candidate should have minimum 5 years of experience in SoC Verification. - This position is based at our Bengaluru office. - A 15 years full time education is required.

15 years full time education