Functional Verification Engineer

Project Role : Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : Functional Test Planning
Good to have skills : NA
Minimum 5 year(s) of experience is required
Educational Qualification : 15 years full time education

Summary: As a Functional Verification Engineer, you will engage in the development and execution of testbenches aimed at verifying the functional correctness of digital designs at both the block and system levels. Your typical day will involve creating constrained-random, directed, and coverage-driven tests using languages such as SystemVerilog and UVM. You will also collaborate closely with design and architecture teams to identify corner cases, ensuring that complete functional coverage is achieved prior to tape-out. This role requires a proactive approach to problem-solving and a commitment to maintaining high standards of quality in verification processes. Roles & Responsibilities: - Expected to be an SME. - Collaborate and manage the team to perform. - Responsible for team decisions. - Engage with multiple teams and contribute on key decisions. - Provide solutions to problems for their immediate team and across multiple teams. - Mentor junior team members to enhance their skills and understanding of functional verification processes. - Continuously evaluate and improve verification methodologies to enhance efficiency and effectiveness. Professional & Technical Skills: - Must Have Skills: Proficiency in Functional Test Planning, Retail industry experience (preferably in the US/CAN region), Order management experience, E-commerce testing experience (Tax, Fraud, Payments, Customer Care) - Strong knowledge of SystemVerilog and UVM for testbench development. - Experience in creating constrained-random and directed tests. - Ability to analyze and identify corner cases in digital designs. - Familiarity with coverage-driven verification techniques. Additional Information: - The candidate should have minimum 5 years of experience in Functional Test Planning. - This position is based at our Bengaluru office. - A 15 years full time education is required.

15 years full time education