Verification Engineer

Your Role

As a SoC GLS Verification Engineer, you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design and verification teams to ensure functional correctness, timing accuracy, and overall quality of silicon-ready designs. Your expertise in GLS methodologies and debugging will be critical in delivering high-performance, reliable SoCs.

In this role, you will:

• Perform GLS using Zero Delay, SDF, and Post-Layout GLS (PAGLS) techniques.
• Debug and resolve issues in gate-level simulations to ensure timing and functional correctness.
• Develop and maintain SystemVerilog/UVM testbenches for GLS environments.
• Collaborate with cross-functional teams to integrate and validate SoC components.
• Use tools like Synopsys Verdi and Cadence NC-Sim for simulation and waveform analysis.
• Contribute to verification planning, execution, and closure for SoC projects.
• Ensure alignment with SoC architecture and design specifications.

Your Profile

• Total Experience: 5–7 years in SoC verification, with 3+ years of GLS-specific experience.
• GLS Expertise: Hands-on with Zero Delay, SDF, and PAGLS flows.
• Debugging Skills: Strong analytical and debugging capabilities in gate-level environments.
• Verification Knowledge: Proficient in SystemVerilog, UVM, and testbench development.
• EDA Tools: Experience with Synopsys Verdi, Cadence NC-Sim, and related tools.
• Architecture Understanding: Solid grasp of SoC architecture, integration, and verification flows.

What You’ll Love About Working Here

We offer a collaborative and innovation-driven environment where engineers are empowered to solve complex challenges. You’ll benefit from:

• Exposure to cutting-edge SoC technologies and verification methodologies.
• Flexible work arrangements and a healthy work-life balance.
• A culture of continuous learning with access to training and certifications.
• Opportunities to work with industry experts and grow your technical expertise.