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Position Overview
We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASIC’s. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking chips.
Responsibilities
Qualifications
ME/BE with a minimum of 8-15 years of experience.
Hands-on knowledge of System Verilog and Verilog is mandatory.
Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
Proven expertise in designing and optimizing scheduling and QoS mechanisms.
Experience with Ethernet and IP protocols.
Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences
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