physical design engineer

Astera Labs

<div><div><p>Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL&reg;, Ethernet, NVLink, PCIe&reg;, and UALink&trade; semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.</p></div><p>
As an Astera Labs Principal Physical Design Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.</p>
<p><b>
Key Responsibilities</b></p>
<ul>
<li>Independently drive PnR activities from RTL to GDS, ensuring robust signoff across complex SoCs or sub-systems.</li>
<li>Identify RTL issues early and work with frontend team on resolution.</li>
<li>Hands-on experience with various custom clocking techniques.</li>
<li>Experience with high-speed designs with serdes/ddr IPs.</li>
<li>Good understanding of PnR tool and signoff flows like Extraction, STA, Formality, EM-IR and DRC/LVS etc</li>
<li>Hands-on experience with ECO flow using PT DMSA and hyperscale models for bigger chips</li>
<li>A good understanding of SDC constraints, be able to interact with design team on constraints refinement.</li>
<li>Work with top level owners on defining and managing I/O timing budgets across hierarchical designs.</li>
<li>Knowledge of different ways to build hierarchical design (black-box model, ETM or abstract model etc).</li>
<li>Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.</li>
</ul>
<p><b>Basic Qualifications</b></p>
<ul>
<li>Bachelor's in Electrical Engineering or Computer Science required; Master's preferred.</li>
<li><ul><li>10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.</li></ul></li>
<li>Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.</li>
<li>Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).</li>
<li>Proficiency with Cadence and/or Synopsys physical design/STA toolchains.</li>
<li>Strong scripting ability (Tcl, Python, Perl).</li>
<li>Ability to work independently with strong prioritization and a professional, customer-focused mindset.</li>
</ul>
<p><b>Preferred Experience</b></p>
<ul>
<li>Familiarity with high-speed SERDES and Ethernet PHY timing challenges.</li>
<li>Knowledge of ECO methodologies, DFT tools, and test coverage analysis.</li>
<li>Experience working with IP vendors for both RTL and hard-macro integration.</li>
<li>SystemVerilog/Verilog familiarity.</li>
</ul><div><p>
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div></div>

Principal Physical Design Engineer

Zenium Cables Pvt Ltd

<p>Komal Healthcare is looking for Orthopedic Implant Design Engineer for our manufacturing at Bhayandar East, Mumbai.</p><p><b>Requirements</b><br/><b>Education:</b> Bachelor&rsquo;s degree in Mechanical Engineering, Biomedical Engineering, or related field.<br/><b>Software Proficiency:</b> SolidWorks, NX, Creo, or AutoCAD.<br/><b>Experience:</b> Minimum 3+ Years in similar industry<br/><b>Salary: </b>Rs. 35000/- to 50000/- Per Month (No bar for right candidate)</p><p>Job Description:<br/>An Orthopedic Implant Design Engineer develops, validates, and optimizes musculoskeletal implants (hip, knee, spine, extremities) and surgical instruments using CAD (SolidWorks, NX) and, frequently, Patient-Specific Modeling (PSM). They ensure regulatory compliance (ISO 13485) and design for manufacturability (DFM).</p><ul><li><b>CAD Design &amp; Modeling:</b> Creating detailed 3D models of implants and specialized surgical instrumentation.</li><li><b>Simulation &amp; Analysis:</b> Utilizing FEA (Finite Element Analysis) and simulation software to test implant durability and performance.</li><li><b>Regulatory &amp; Safety:</b> Ensuring compliance with industry standards (e.g., FDA, ISO 13485) and generating necessary technical documentation.</li><li><b>Manufacturing Knowledge:</b> Applying DFM/DFA (Design for Manufacturing/Assembly) principles to optimize production.</li><li><b>Collaboration:</b> Working with surgeons and clinical teams to translate clinical needs into design specifications. www.glassdoor.co.in +6.</li></ul><p><b>Common Work Settings</b><br/>Orthopedic companies focus on joint replacement, Trauma/Extremity, and Spine devices.</p><p>Interested candidates may apply here on share resume on what's app no. 9049252888</p><p>Job Types: Full-time, Permanent</p><p>Pay: ₹35,000.00 - ₹50,000.00 per month</p><p>Work Location: In person</p>

Orthopedic Implant Design Engineer

YO IT CONSULTING

<div><p><b>Job Description</b></p>
<p><b>Title</b>: Sr. Layout Designer<br>
<b>Experience</b>: 10 to 15 years<br>
<b>Location</b>: USA - Austin (Austin, TX, five days a week.)</p>
<p><b>Visa Status :Will sponsor H1-B</b></p>
<p><b>Must Have:</b></p>
<ul><li>10+ years of industry experience in analog/mixed-signal layout design in advanced process nodes (2nm&ndash;16nm, preferably TSMC).</li></ul>
<ul><li>Proven track record designing layouts for high-speed ADC/DAC and SerDes circuits, with deep understanding of timing, matching, shielding, and electromigration considerations.</li></ul>
<ul><li>Hands-on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and solid understanding of schematic-to-layout (S2L) flow.</li></ul>
<ul><li>Experience with FinFET and/or Gate-All-Around (GAA) process technologies.</li></ul>
<ul><li>Strong understanding of analog layout techniques: current mirrors, differential pairs, resistors, capacitors, biasing, shielding, guard rings, and ESD structures.</li></ul>
<ul><li>Experience leading tape-outs, including design documentation, sign-off checks, and cross-team coordination.</li></ul>
<ul><li>Good communication skills, both written and oral. The ability to articulate their thought process, and lead junior members is important.On-site in Austin, TX, five days a week.</li></ul>
Masters in Electrical Engineering, Computer Engineering, or related field.
<p><b>Role And Responsibilities:</b></p>
<p>Own the physical layout design of high-performance ADC/DAC, SerDes, and analog/mixed-signal circuits across advanced nodes (2nm&ndash;16nm).</p>
<p>Plan, and implement layout design for high-speed, low-noise analog blocks, ensuring signal integrity, matching, symmetry, and optimal parasitics.</p>
<p>Closely Collaborate with circuit designers to achieve aggressive power, performance, and area (PPA) targets, while maintaining design-for-manufacturability (DFM) best practices.</p>
<p>Work with Cadence Virtuoso and Synopsys Verification tools [to perform layout design, verification, and integration.</p>
<p>Drive floorplanning and analog block partitioning, ensuring effective power grid design, guard ring placement, and substrate isolation techniques.</p>
<p>Partner with foundry and CAD teams to optimize design flows for TSMC FinFET and Gate-All-Around (GAA) process nodes.</p>
<p>Conduct LVS, DRC, ERC, and parasitic extraction (PEX) reviews and close layout verification loops.</p>
<p>Participate in top-level integration and tape-out, ensuring all layout data and GDS handoffs meet signoff requirements.</p>
<p>Provide technical mentorship to fellow engineers and help define layout design methodologies and automation improvements.</p>
<p>Minimum Qualifications</p>
<p>10+ years of industry experience in analog/mixed-signal layout design in advanced process nodes (2nm&ndash;16nm, preferably TSMC).</p>
<p>Proven track record designing layouts for high-speed ADC/DAC and SerDes circuits, with deep understanding of timing, matching, shielding, and electromigration considerations.</p>
<p>Hands-on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and solid understanding of schematic-to-layout (S2L) flow.</p>
<p>Experience with FinFET and/or Gate-All-Around (GAA) process technologies.</p>
<p>Strong understanding of analog layout techniques: current mirrors, differential pairs, resistors, capacitors, biasing, shielding, guard rings, and ESD structures.</p>
<p>Experience leading tape-outs, including design documentation, sign-off checks, and cross-team coordination.</p>
<p>Strong analytical, problem-solving, and communication skills.</p>
<p>Self-motivated engineer eager to work in a fast-paced start-up environment, adaptable to evolving project demands.[EF5]</p>
<p><b>Preferred Qualifications</b></p>
<p>Familiarity with Mentor/Siemens Calibre verification tools and scripting (Skill, Python, or Tcl) for layout automation.</p>
<p>Exposure to floorplanning and top-level chip integration for complex mixed-signal SoCs.</p>
<p>Experience optimizing for signal integrity, IR drop, and thermal effects in high-speed designs.</p></div>

Sr Layout Designer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:<div></div><div><b><br>
THE ROLE:</b></div><div>
The focus of this role is to analyze power consumption of SOC for different use cases and identify optimization opportunities, generate power optimal recipe for physical design teams, help design teams build power optimal design at architecture level, RTL level.</div><div></div><div><b><br>
THE PERSON:</b></div><div>
You have a passion for modern, complex processor architecture, digital design, and low power design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.</div><div></div><div><b><br>
KEY RESPONSIBILITIES:</b></div><ul><li>
Collaborate with architects, hardware engineers, and firmware engineers to understand the use cases for which design need to be optimized, power features being implemented.</li><li>
Build test plan documentation, for sub-set of use case tests</li><li>
work with simulation teams to get required fsdb for power analysis and optimize design.</li><li>
Run PTPX to generate power numbers, analyze power consumption, correlate the power with older project or IP level power projections.</li><li>
Analyze power consumption in design, identify ways implement a power optimal design, share recepie with physical design teams.</li></ul><div></div><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
Proficient in Power analysis and PTPX flow with 7+ years of exp</li><li>
Proficient in power optimal design implementation at Physical design stage</li></ul><ul><li>
Proficient in using physical design flows, ICC, Fusion compiler, Innovus</li><li>
Experienced in battery life workloads and analysis, test definition for power usecases</li><li>
Experienced with Verilog, System Verilog, C, and C++</li><li>
Experience using fsdbs, vcs simulation, formality endpoint mapping</li><li>
Experience with scripting languages perl, python, etc..</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors or Masters degree in computer engineering/Electrical Engineering</li></ul><p></p><p><br>
#LI-PK2</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div><div></div><div><i><br>
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available </i><i>here.</i></div><div></div><div><i><br>
This posting is for an existing vacancy.</i></div></div>

SoC Power Analysis Engineer- PTPX/Low Power Physical Design

Siliciom Technologies

<div></div><div><div><div><ul><li>ASIC</li><li>
Location: Bangalore</li><li>
Experience: 3 - 5 Years</li></ul><h5 class="jobSectionHeader"><b>
Required Skills &amp; Knowledge:</b></h5><ul><li>
B. Tech / M. Tech with hands on experience into Physical verification at block-level&amp; chip-level.</li><li>
DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off experience is a must.</li><li>
Experience using Synopsys ICC Tool.</li><li>
Tape-out experience of multiple complex chips at 14 nm or below is required.</li><li>
Experience with Mentor Calibre or Synopsys ICC and ICV is a must.</li><li>
Programming experience in tcl, Perl or C.</li><li>
Proficient in planning for and addressing electrical considerations throughout the design process (EM, IR, Noise, etc.).</li><li>
Physical verification flow automation exposure will be an added advantage.</li></ul><p>
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com</p></div></div></div>

Physical Verification Engineer:

<div></div><div><div><div><ul><li>ASIC</li><li>
Location: Bangalore</li><li>
Experience: 3 - 5 Years</li></ul><h5 class="jobSectionHeader"><b>
Required Skills &amp; Knowledge:</b></h5><ul><li>
Btech/Mtech Electronics/Electrical engineering</li><li>
Experience in Analog Mixed-signal layout and verification of high-speed digital and/or DDR IOs, Critical signal inclusion.</li><li>
Advanced understanding of Deep submicron effects and mitigation.</li><li>
Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies.</li><li>
Solid understanding of CMOS and FinFETlayouts and process technology in 28nm and smaller.</li><li>
Good understanding of basic ESD and latchup layout design considerations.</li><li>
Familiarity with ASIC physical design flow:LEF generation, Place &amp; Route &amp; understanding of top level verification flow, DRC/LVS, LPE.</li><li>
Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc</li><li>
Scripting skills for layout automation is a plus</li><li>
emote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership.</li><li>
Excellent written and verbal communication skills in interactions with customers, and internal development teams.</li></ul><p>
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com</p></div></div></div>

Analog Layout Engineer:

Qualcomm

<div><h2 class="jobSectionHeader"><b>Company:
</b></h2>Qualcomm Technologies, Inc.
<p></p><h2 class="jobSectionHeader"><b>Job Area:
</b></h2>Engineering Group, Engineering Group &gt; CPU Engineering
<p></p><p><b>General Summary:
</b></p><div><p>This individual leads, plans, synthesizes ambiguous or conflicting requirements, and performs the complex responsibility of the leveraging deep understanding and knowledge of microprocessor architecture, computer architecture, logic design, circuits, and/or physical design to develop and/or verify advanced CPU designs. Interfaces with all disciplines to design, verify, and implement multi-core Computer Processing Unit (CPU) operations for QCT. Applies CPU architectural, micro-architecture, and design verification concepts to deliver high performance and low power CPUs. Evaluates all aspects of the design process from concept to productization that meet customer and industry standards. Anticipates, identifies, and solves complex problems to ensure design completeness, functionality, power, and performance. Collaborates with colleagues within and outside of team and collects feedback during design and verification reviews to understand requirements, specifications, and trade-offs (e.g., performance, power, cost, functionalities, etc.) in order to accomplish product goals. Drives continuous self-improvement through building knowledge from existing processes and experiences, industry trends, research, and advances in CPU-related technology; shares knowledge with others on their team and helps less experienced engineers understand and apply advanced concepts. Participates in all phases from design concept to productization including, architecture definition, feasibility, pre-silicon design and verification, and post-silicon validation. Writes clear and detailed technical documentation such as feature descriptions, architectural descriptions, verification test plans, and implementation details for complex designs. Act as a strong contributor at design reviews and project meetings and communicates and implements a development plan.
</p><p></p><div><p>Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field. Will also accept a Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and five (5) years of progressive experience in a related occupation. Employer will accept any suitable combination of education, training or experience.
</p><p></p><p>Compensation: $161,179.00 - $222,500.00/year
</p></div></div><p></p><div><div><div><div><div><div><div><p><b>Applicants </b>: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
</p></div></div></div></div></div></div></div><p></p><p><b>To all Staffing and Recruiting Agencies </b>: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
</p><p><b>EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
</b></p><p></p><p>Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.<br>
</p><p></p><p>If you would like more information about this role, please contact Qualcomm Careers .</p></div>

Staff CPU Engineer

Search 10000+ Physical design engineer jobs near you this March. New roles added regularly across leading industries. Apply today.