physical design engineer

Apple

At Apple we work every single day to craft products that enrich people&rsquo;s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple&rsquo;s customers every single day. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be required to do physical designs of outstanding PHY design. 
 
Description 
 
As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration. 
 
Preferred Qualifications 
 
Deep design experience in high PHY and/or SOC designs. 
 
Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place &amp; Route. 
 
Experience in developing and implementing Power-grid and Clock specifications. 
 
Strong understanding of all aspects of Physical construction, Integration and Physical Verification. 
 
Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design &amp; Synthesis tools. 
 
Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools. 
 
Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level. 
 
Minimum Qualifications 
 
Bachelors of Science in Electrical Engineering. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $220,900, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Physical Design Engineer

Google

<div>Note: Google's hybrid workplace includes remote and in-office roles. By applying to this position you will have an opportunity to share your preferred working location from the following: 
 
In-office locations: Sunnyvale, CA, USA. 
Remote location(s): Florida, USA.<h3 class="jobSectionHeader">
Minimum qualifications:</h3><ul>
<li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 
</li>
<li>10 years of experience managing third-party vendor engagements and technical delivery schedules in an ASIC design environment.</li>
<li>Experience in design synthesis, Logic Equivalence Checking (LEC) (e.g., Formality or Conformal), and Static Timing Analysis (STA).</li>
<li>Demonstrated ability to debug technical issues within the RTL-to-netlist flow and collateral handoff processes.</li></ul> 
<h3 class="jobSectionHeader">
Preferred qualifications:</h3><ul>
<li>Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 
</li>
<li>Experience in low power design implementation including UPF/CPF and multi-voltage domains. 
</li>
<li>Experience with scripting languages such as Tcl or Python to automate and improve design workflows.</li>
<li><div>Familiarity with hierarchical Place and Route (PNR) construction, timing closure, and relevant design rules in modern process nodes.</div></li>
</ul><div><h2 class="jobSectionHeader">About the job</h2>
In this role, you&rsquo;ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You&rsquo;ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The Google Cloud TPU team is responsible for designing and delivering the custom silicon that powers Google's AI/ML infrastructure. Our physical design team transforms RTL into large-scale, high-performance ASICs. This role serves as a technical authority for physical design execution, establishing a holistic methodology that ensures both schedule predictability and a competitive final product across our portfolio of reticle-scale designs.<div>
In this role, you will lead technical engagements with third-party vendors to drive the successful implementation of complex ASICs. You will be the primary point of contact for vendor workstreams, managing the delivery of critical design collateral and ensuring all quality-of-results benchmarks are met. You will bridge the gap between internal design efforts and external execution, overseeing the transition of select blocks through the physical design workflow to ensure tapeout readiness.</div> 
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.</div><div><h2 class="jobSectionHeader">
Responsibilities</h2><ul>
<li>Lead and manage technical engagements with third-party vendors, overseeing project workstreams and schedules to ensure timely execution. 
</li>
<li>Manage the handoff of design collateral to external partners, performing quality checks to ensure data integrity and methodology alignment. 
</li>
<li>Drive design synthesis and Logic Equivalence Checking (LEC) using industry-standard tools such as Formality or Conformal.</li>
<li>Perform basic Static Timing Analysis (STA) and debug issues arising in synthesis, LEC, etc. 
</li>
<li>Oversee internal teams performing targeted physical design work on select blocks to ensure success before vendor-side signoff and artwork release. 
</li>
</ul></div>Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.</div>

Staff Physical Design Engineer

<div>At Apple, we believe our products begin with our people. By hiring a diverse team, we drive creative thought. By giving that team everything they need, we drive innovation. By hiring incredible engineers, we drive precision. And through our collaborative process, we build memorable experiences for our customers! These elements come together to make Apple an amazing environment for motivated people to do the greatest work of their lives. You will become part of a hands-on development team that sets the standard in cultivating excellence, creativity and innovation. Come help us design the next generation of revolutionary Apple products. 
 
We are looking for a forward-thinking and unusually talented engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft and implement methodologies and solutions with a high impact on upcoming products that will delight and inspire millions of Apple&rsquo;s customers every single day. In this role, you will be directly involved in our physical design machine learning efforts, collaborating right alongside our internal multi-functional teams, and using your expertise in machine learning and physical design to ensure that our SOCs achieve the optimal Power, Performance, and Area (PPA). We account for every nano watt, every nano meter, and every pico second. 
 
Description 
 
As a member of the physical design machine learning architecture team, you will be part of a dynamic team that is building the most efficient application processors on the planet, powering the next generation of Apple products. 
 
<ul><li>You will use your experience in physical design and machine learning to solve very hard and unique problems.</li></ul> 
<ul><li>Your work will directly impact vast areas of the flow including RTL design, logic synthesis, floor planning, power/clock distribution, place and route, timing/noise analysis, power/thermal analysis, voltage drop analysis, design for manufacturing/yield, and beyond.</li></ul> 
<ul><li>You will collaborate cross functionally with design, power, post silicon, CAD, software and machine learning teams in an engaging and rewarding environment.</li></ul> 

Preferred Qualifications 
 
Practical experience and knowledge in advanced machine learning algorithms like GNNs, VAEs, transformers, diffusion models, LLMs. 
 
Excellent programming skills in Python and C/C++. 
 
Master's or PhD with relevant publications in Machine Learning and/or EDA algorithms. 
 
Excellent communication and organizational skills. 
 
Minimum Qualifications 
 
Minimum BS and 3+ years of relevant industry experience 
 
Understanding of optimization algorithms, complex data structures, and/or linear algebra. 
 
Understanding of VLSI fundamentals, including physical design. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.</div>

Physical Design Engineer, Machine Learning

Amazon Web Services

<div><h2 class="jobSectionHeader">DESCRIPTION</h2><div>
Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power today's AI workloads across datacenters worldwide. As an ASIC Design Methodologies and Infrastructure Engineer, you'll play a foundational role in the project by automating design flows and building large-scale solutions that accelerate silicon development and we're just getting started here at Amazon! 
 
We're looking for a strong engineer who is passionate about creating design flows and automation flows that enhance both the productivity and quality of our design team. The ideal candidate brings proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving and automating flows. In this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality. 
Key job responsibilities 
 
Core Responsibilities: 
 
<ul><li>Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards.</li><li>Enhance and build design flows to boost the overall productivity of design teams.</li><li>Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.</li></ul> 
About the team 
Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago&mdash;even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help
 
 
Diverse Experiences 
Annapurna values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn&rsquo;t followed a traditional path, or includes alternative experiences, don&rsquo;t let it stop you from applying. 
 
Work/Life Balance 
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there&rsquo;s nothing we can&rsquo;t achieve in the cloud. 
 
Inclusive Team Culture 
Here at Annapurna, it&rsquo;s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon conferences, inspire us to never stop embracing our uniqueness. 
 
Mentorship &amp; Career Growth 
We&rsquo;re continuously raising our performance bar as we strive to become Earth&rsquo;s Best Employer. That&rsquo;s why you&rsquo;ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
</div><h2 class="jobSectionHeader">BASIC QUALIFICATIONS</h2><ul><li>7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience</li><li>7+ years of digital design in communication systems experience</li><li>7+ years of full-custom analog or RF layout experience</li><li>7+ years of wireless communications systems and implementation experience</li><li>8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience</li><li>7+ years of verification in communication systems experience</li><li>5+ years of UVM, C, System C, and scripting experience</li></ul><h2 class="jobSectionHeader">
PREFERRED QUALIFICATIONS</h2><ul><li>Master's degree or Ph.D. degree in Electrical Engineering or related field</li><li>Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs</li><li>Experience with modern ASIC/FPGA design and verification tools</li><li>Experience with SOC bring-up and post-silicon validation</li></ul> 
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. 
 
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. 
 
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner. 
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life &amp; AD&amp;D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits. 
USA, CA, Cupertino - 183,000.00 - 247,600.00 USD annually 
USA, TX, Austin - 159,200.00 - 215,300.00 USD annually</div>

Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

Cadence Design Systems

<div><h2 class="jobSectionHeader">At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.</h2>
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world&rsquo;s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage<ul><li>
The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.</li><li>
Cadence&rsquo;s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.</li><li>
The unique &ldquo;One Cadence &ndash; One Team&rdquo; culture promotes collaboration within and across teams to ensure customer success.</li><li>
Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.</li><li>
You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other&mdash;every day.</li></ul>
Job responsibilities:
Job Description: Analog Layout Design
Work Location: Hyderabad
Work Experience : 5 &ndash; 7 years or equivalent relevant experience.
CV to send K Madhu Prasad kmadhup@cadence.com
Responsibilities:<ul><li>
Custom layout design for NextGen, high-speed IPs like SerDes/DDR/GDDR/LPDDR/ Pcie/D2D/HBM/Ucie/Chiplets and much more which are yet on the horizon&hellip;</li><li>
Understanding requirements from different teams and stakeholders be it circuit-design, digital, packaging or foundry and work with a co-creation mindset to successfully deliver Analog Macros *(depending upon level of exp).</li><li>
Perform physical verifications<ul><li>
Full Spectrum Verifications as per foundry requirements.</li><li>
Flavors of DRC</li><li>
Various Electrical check / LVS /EMIR and Reliability Compliance.</li></ul></li><li>
Based on expertise level, would be required to not just contribute as an individual contributor, but wear a hat of a leader to lead a team of engineers towards a successful IP delivery.</li><li>
To be agile enough and adapt-with-ease with changing market, client, technology and foundry needs.</li></ul>
Requirements<ul><li>Hands-on experience in analog/mixed-signal layout design.</li><li>It&rsquo;s expected to have ownership and hands on high-speed products, classical analog products.</li><li>Hands on layout experience in various analog IP like High-speed Analog (Serdes), Data converters, power management and PLL etc.</li><li>Having worked on latest technology nodes like 18a, 2nm, 3nm, 5nm, 7nm and below, is desired.</li><li>Knowledge of various analog layout techniques, floorplan constraints and IP integration at chip level scenario.</li><li>Hands on layout experience in various analog modules like Op-amps, Bandgaps, Data converters, LDO and PLL etc.</li><li>Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,</li><li>Knowledge of various analog layout techniques like matching, shielding etc.,</li><li>Must have good communication skills and should be team player.</li><li>Scripting and automation experience is a plus.</li><li>Good communication skills, documentation, and presentation skills.</li><li>Strong analytical and problem-solving skills.</li></ul>
********************************************************************************************************************************************
Qualifications<ul><li>
BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent</li></ul>
Behavioral skills required.<ul><li>
Must possess strong written, verbal and presentation skills.</li><li>
Ability to establish a close working relationship with both customer peers and management.</li><li>
Explore what&rsquo;s possible to get the job done, including creative use of unconventional solutions.</li><li>
Work effectively across functions and geographies</li><li>
Push to raise the bar while always operating with integrity.</li></ul>
Regards
Madhu
kmadhup@cadence.com<h2 class="jobSectionHeader">
We&rsquo;re doing work that matters. Help us solve what others can&rsquo;t.</h2></div>

Lead Design Engineer ( Layout Design )

City of Englewood, CO

<div><h3 class="jobSectionHeader">POSITION SUMMARY</h3>

The Capital Project Engineer serves as a project manager, overseeing the coordination and design of various public improvements and city capital construction projects from conceptual planning, through detailed design, into construction and final completion. These may include: pavement maintenance activities, street reconstruction, utility replacement or rehabilitation, sidewalks, trails &amp; pedestrian ramps, alleys, bridges, drainage, flood &amp; erosion control, parks, and miscellaneous infrastructure repairs. Designs small- and medium-size improvements. Reviews consultant plans on large projects. Makes decisions and recommendation on major projects, and coordinates planning and design activities with staff and operations. Communicates and seeks input from the community. 

<h3 class="jobSectionHeader">
REPORTING RELATIONSHIPS</h3>

Reports to: Engineering Manager

Direct Reports: None 

<h3 class="jobSectionHeader">
DUTIES AND RESPONSIBILITIES</h3>

The listed examples of work are not intended to be all-inclusive. They may be modified with additions, deletions, or changes as necessary.
<h4 class="jobSectionHeader">
Essential Duties &amp; Responsibilities</h4>
<ul><li>Manages and performs the planning, design and implementation of various infrastructure maintenance &amp; capital projects.</li>
<li>Designs small- and medium-size public infrastructure projects; prepares plans and specifications; prepares construction cost estimates.</li>
<li>Develops requests for proposals, scopes of work, planning &amp; bid documents. Procures services and contractors in accordance with the city&rsquo;s Procurement Policy. Evaluates responses and makes recommendations regarding consultant and contractor selection.</li>
<li>Assists with oversight of Pavement Management Program; helps to identify and plan short- and long-range improvements based on available funding and asset management data; makes and recommends resource decisions by considering life-cycle costs, funding constraints and cost-benefit analyses.</li>
<li>Assists other departments and divisions in the preparation of cost estimates for projects.</li>
<li>Assists with contract administration, inspections, design calculations, property research and preparation of graphic presentations; initiates and prepares project reports and records</li>
<li>Directs the work performed by consultants on large projects</li>
<li>Prepares proactive communications to the public and other stakeholders for assigned projects; responds to inquiries from the public, utilities, other government agencies, and contractors</li>
<li>Works with other governmental agencies, citizen groups, and industry representatives on projects and programs.</li>
<li>Assists Construction Manager in reviewing and responding to proposed changes to contract requirements and makes decisions or recommendations on appropriate action.</li>
<li>Contributes to the development and implementation of departmental goals, objectives, policies, procedures, and service standards.</li>
</ul><h4 class="jobSectionHeader">Other Duties &amp; Responsibilities</h4>
<ul><li>Performs other duties as assigned and required.</li></ul> 

<h3 class="jobSectionHeader">
PREPARATION AND TRAINING</h3>
<h4 class="jobSectionHeader">Education</h4>
<ul><li>Bachelor&rsquo;s Degree in Civil Engineering.</li>
</ul><h4 class="jobSectionHeader">Work Experience</h4>
<ul><li>Capital Project Engineer I: 0-5 years of experience managing and/or designing infrastructure projects</li>
<li>Capital Project Engineer II: Minimum of 5 years of experience managing and/or designing infrastructure projects;</li>
</ul><h4 class="jobSectionHeader">Certifications/Licensures</h4>
<ul><li>Capital Project Engineer I: State of Colorado Engineer Intern (EI) enrollment or ability to obtain within six months of employment.</li>
</ul><ul><li>Capital Project Engineer II: State of Colorado Professional Engineer (PE) license or ability to obtain within six months of employment.</li>
</ul><h4 class="jobSectionHeader">Required Driver's License</h4>
<ul><li>Valid Colorado driver&rsquo;s license and a clear or acceptable MVR</li>
</ul>
An equivalent combination of education, training and relevant job experience may be substituted. 

<h3 class="jobSectionHeader">
KNOWLEDGE, SKILLS, AND ABILITIES</h3>
<h4 class="jobSectionHeader">Knowledge</h4>

Basic to Advanced knowledge of:
<ul>
<li>Engineering design</li>
<li>Project management</li>
<li>Mapping and drawings</li>
<li>Municipal infrastructure Basic to Working knowledge of:</li>
<li>Contracts and project delivery</li>
<li>Regulations and codes</li>
<li>Permitting</li>
<li>Applications software for Windows environment, Microsoft Office preferred</li>
</ul><h4 class="jobSectionHeader">Skills and Abilities</h4>
<ul><li>Computer Skills - Strong skills needed to work in a high technology environment. AutoCAD, Microstation, or other design platform experience preferred.</li>
<li>Communication - Strong skills required to work with the public &amp; other project stakeholders to reach consensus; prepare and deliver presentations; manage consultants. Strong written skills needed to produce Council communications and technical memorandums.</li>
<li>Analytical - Strong skills needed for data analysis. Advanced skills needed for design computations and equations.</li>
<li>Project Management &ndash; Basic to Advanced skills needed to schedule and track progress of infrastructure projects. Also needed for the assembly of work groups.</li>
<li>General Management - Strong skills needed for resource management.</li>
<li>Mathematical - Strong skills needed for field measurement and specifications, quantity estimates and pay items, and complex engineering calculations.</li></ul> 

<h3 class="jobSectionHeader">
SALARY RANGE</h3>
<ul><li>Capital Project Engineer I: $75,761 - $113,506</li>
<li>Capital Project Engineer II: $85,508 - $128,262</li></ul> 

<h3 class="jobSectionHeader">
BENEFITS</h3>

The City of Englewood offers a comprehensive benefits package including but not limited to:
<ul>
<li>Medical, Dental, and Vision Plans</li>
<li>Retirement Plans</li>
<li>Paid Time Off</li>
<li>Paid Sick Leave</li>
<li>12 Paid Holidays</li>
</ul>
More information about our benefits can be found here 

<h3 class="jobSectionHeader">
WORKING CONDITIONS</h3>

Work is performed in a standard office environment, requiring sitting for extended periods of time, and occasional light lifting (up to 15 lbs.). Job requires visual and physical capabilities to work on computers and associated equipment for prolonged periods of time (4-6 hours daily). Job requires the physical dexterity of movement sufficient to visit construction sites and make field observations while adhering to typical Personal Protective Equipment (PPE) requirements. 

<h3 class="jobSectionHeader">
PRE-EMPLOYMENT SCREENINGS</h3>

This position is subject to a mandatory background screening. 

<h3 class="jobSectionHeader">
APPLICATION DEADLINE</h3>

Open until filled.</div>

Capital Project Engineer I/II

Gulf Companies

<div>
 
 Description
 
 
 
 
 Position Title:
 
 Senior Pipeline Engineer
 
 
 
 Location:
 
 Doha, Qatar
 
 
 Gulf Companies has served the global energy industry since 1953 by supporting the complete project lifecycle and developing valued business partnerships to ensure the success of the project. Our worldwide experience and multi-disciplined capabilities encompass all aspects of Engineering, Procurement, Construction Management, Field Inspection, GIS Integrity, Staffing Services and more.
 
 
 
 Position Description
 
 
 
 The Senior Pipeline Engineer is expected to be able to function as the Lead Pipeline Engineer on smaller projects and be responsible for all discipline technical and scheduling matters pertaining to the assigned project. He/she receives little supervision and in turn may provide technical guidance, as required, to lower classified personnel on assignments. Work is periodically reviewed by Chief Pipeline Engineer for accomplishment of objectives.
 
 
 
 Essential Functions
 
 
 
 <ul>
 <li>
 Function as the Lead Pipeline Engineer on smaller projects.
 </li>
 <li>
 Independently prepares or reviews discipline project specifications.
 </li>
 <li>
 Independently prepares technical bid evaluations for equipment, materials, bulk material and subcontracts in cooperation with Procurement Department.
 </li>
 <li>
 Reviews and approves vendor drawings.
 </li>
 <li>
 Independently perform typical pipeline engineering calculations.
 </li>
 <li>
 Independently prepares requisitions for inquiry in support of purchasing equipment and materials.
 </li>
 <li>
 Prepares Pipe tally and communicates the design changes internally
 
 
 </li>
 </ul>
 
 Requirements
 
 
 
 
 Qualifications
 
 
 
 <ul>
 <li>
 Typically, minimum 10 years of experience in pipeline engineering, pipeline operations, or pipeline construction
 </li>
 <li>
 Familiar with all relevant codes and regulations
 </li>
 <li>
 Familiar with industry practices and permitting requirements for pipeline design and construction
 </li>
 <li>
 Strong interpersonal, organizational and leadership skills
 </li>
 <li>
 Strong verbal and written communication skills
 </li>
 <li>
 Proficient with computers in an engineering environment. Knowledge of GIS is an asset.
 </li>
 <li>
 Bilingual is an asset
 </li>
 <li>
 Qatar Engineering license (MME/MMUP/UPDA)
 
 
 </li>
 </ul>
 
 Education
 
 
 
 <ul>
 <li>
 BS in Engineering
 
 
 </li>
 </ul>
 
 Competencies
 
 
 
 <ul>
 <li>
 Results oriented
 </li>
 <li>
 Customer focused
 </li>
 <li>
 Focused on accuracy and quality of work
 
 
 </li>
 </ul>
 
 Work Environment/Physical Demands
 
 
 
 <ul>
 <li>
 Working conditions are normal for an office environment.
 </li>
 <li>
 Frequent sitting and operating a computer.
 </li>
 <li>
 Must be able to use body members to work, move or carry objects or office materials.
 </li>
 <li>
 Must be able to exert up to 10 pounds of force occasionally.
 </li>
 <li>
 Physical demands requirements are at levels of those for sedentary work.
 </li>
 </ul>
</div>

SR. PIPELINE ENGINEER-DOHA, QATAR

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