physical design engineer

Credo Semiconductor

<div>Credo is engineering the future of high-speed connectivity for the AI-driven world. With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers. 
Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure. 
At Credo, you&rsquo;ll be part of a team of world-class technologists and engineers that thrive on pushing the limits of what&rsquo;s possible for some of the world&rsquo;s most important companies. Our portfolio includes cutting edge solutions including our software, optical DSPs, PCIe/CXL products, SerDes IP, and advanced Active Electrical Cables (AECs) all designed for maximum performance, energy efficiency, and scalability. 
We foster a culture of technical excellence, collaboration, and continuous learning, where your ideas can shape the future of connectivity. From silicon architects to systems engineers, every role at Credo contributes to solving real-world problems at scale. 
Join us and help us architect the next generation of disruptive networking technologies &mdash; because at Credo, We Connect. 
About the Role

As a Senior Physical Design Engineer, you will manage all aspects of physical design and implementation for Credo SoC designs. This role involves close collaboration with the local frontend team and PD/integration teams in China and Taiwan to ensure successful tapeouts. 
Responsibilities
<ul>
<li>Lead and drive top-level, IP, and block-level physical implementation from RTL to GDSII.</li>
<li>Focus on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems.</li>
<li>Establish and maintain physical design methodologies, flow automation, chip floorplanning, power/clock distribution, chip assembly, P&amp;R, and timing closure.</li>
<li>Perform static timing analysis, power and noise analysis, and physical verification.</li>
<li>Collaborate closely with frontend and integration teams to ensure successful tapeouts.</li></ul> 


Basic Qualifications
<ul>
<li>BS/MS in EE/CS with 10+ years of hands-on experience in back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies.</li>
<li>Proven track records of handling chip level P&amp;R independently and taping out complex SOC chips under tight schedule pressure.</li>
<li>Experience with 5nm and lower technology nodes.</li>
<li>Proven track records of handling chip level P&amp;R independently and taping out complex SOC chips under tight schedule pressure.</li>
<li>Strong proficiency with EDA tools such as Cadence Innovus and Synopsys Fusipn Compiler.</li>
<li>Solid knowledge on static timing analysis (PrimeTime/Tempus), EM/IR-Drop/crosstalk analysis (PTSI/Voltus/Redhawk), extraction (Quantus/StarRC).</li></ul> 


Preferred Qualifications
<ul>
<li>Familiarity with DRC, Antenna, LVS, ERC tools like Calibre.</li></ul> 


The base salary range for this position is $140,000 &ndash; $170,000 a year. The base salary ultimately offered is determined through a review of education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits. 
Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. 
If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email people@credosemi.com.</div>

Senior Physical Design Engineer

Quest Global

<div>Job Requirements 
 
At Quest Global, it&rsquo;s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place&mdash;to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. 
Key Responsibilities 
We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard. 
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.</div>

Physical Design Engineer

<div>Overview:
<div>
WHAT YOU DO AT AMD CHANGES EVERYTHING</div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.</div>
Responsibilities:
<div>
SMTS SILICON DESIGN ENGINEER</div><div> 
THE ROLE:</div><div>
The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology.</div><div></div><div> 
THE PERSON:</div><div>
The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.</div><div></div><div> 
KEY RESPONSIBILITIES:</div><ul><li>
RTL to GDS2 flow</li><li>
Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC &amp; LVS), Crosstalk Analysis, EM/IR</li><li>
Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk</li><li>
Identify and implement opportunities for improving PPA</li></ul><div> 
PREFERRED EXPERIENCE:</div><ul><li>
12+ years of professional experience in physical design, preferably with high performance designs.</li><li>
Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.</li><li>
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.</li><li>
Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery</li><li>
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation</li><li>
Experience in STA, full chip timing</li><li>
Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl.</li><li>
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams</li><li>
Experience in FinFET &amp; Dual Patterning nodes such as 16/14/10/7/5nm/3nm</li><li>
Excellent physical design and timing background.</li><li>
Good understanding of computer organization/architecture is preferred.</li><li>
Strong analytical/problem solving skills and pronounced attention to details.</li></ul>
ACADEMIC CREDENTIALS:<ul><li>
Qualification: Bachelors or Masters in Electronics/Electrical Engineering</li></ul><div></div><div> 
#LI-PK2</div>
Qualifications:
<div>
Benefits offered are described: AMD benefits at a glance.</div><div></div><div> 
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</div></div>

Lead Physical design, Physical Implementation

Pressure Tech Industrial Machinery Manufacturing

Job Title: Design Engineer &ndash; Fabrication / SPM / Conveyor SystemsLocation: Sharjah, UAESalary: Up to AED 3500 + AccommodationEmployment Type: Full-timeCONTACT - 8925793687Job Summary:We are seeking a Design Engineer with proven experience in fabrication design, SPM (Special Purpose Machines), and conveyor systems. The ideal candidate should have hands-on expertise in AutoCAD, SolidWorks, and mechanical design with a strong understanding of sheet metal fabrication, structural design, and assembly drawings.Key Responsibilities:Design and develop fabrication drawings, SPM machines, and conveyor systems based on project requirements.Prepare accurate 2D and 3D CAD models using AutoCAD, SolidWorks, or equivalent software.Create detailed BOM (Bill of Materials) and ensure design feasibility for manufacturing.Coordinate with fabrication, production, and installation teams to ensure smooth execution.Conduct design calculations, material selection, and structural analysis where required.Optimize designs for cost efficiency, durability, and ease of assembly.Review existing designs and suggest improvements for productivity and performance.Ensure compliance with safety standards and engineering best practices.Requirements:Degree in Mechanical Engineering or a related discipline.2 to 5 years of experience as a Design Engineer in fabrication, conveyor, or SPM industry.Proficiency in AutoCAD, SolidWorks, and other CAD tools.Strong knowledge of fabrication techniques, sheet metal design, and machine assembly.Good understanding of mechanical components, drive systems, and industrial automation layouts.Excellent analytical, problem-solving, and communication skills.Benefits:Salary: Up to AED 3500/monthCompany-provided accommodationOvertime pay as per UAE labor lawJob Type: Full-timePay: Up to AED3,500.00 per month

Design Engineer(Fabrication /SPM)

NVIDIA

<div>
 We are looking for a
 
 Digital/Memory Mask Design Engineer
 
 &ndash; someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.
 
 
 NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life&rsquo;s work , to amplify human creativity and intelligence. As an NVIDIAN, you&rsquo;ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!
 
 
 
 What You'll Be Doing
 
 
 
 <ul>
 <li>
 Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.
 </li>
 <li>
 Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.
 </li>
 <li>
 Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.
 </li>
 <li>
 Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.
 </li>
 <li>
 Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.
 </li>
 <li>
 Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.
 </li>
 <li>
 Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.
 </li>
 <li>
 Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.
 </li>
 <li>
 Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.
 </li>
 <li>
 Excel in resource management, representing the team in technical discussions with customers
 </li>
 <li>
 IP layout will comprise of significant digital components.
 </li>
 <li>
 Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts
 </li>
 <li>
 Follow company procedures and practices for IC layout activities.
 
 
 </li>
 </ul>
 
 What We Need To See
 
 
 
 <ul>
 <li>
 B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ years of proven experience in Memory layout in advanced CMOS process.
 </li>
 <li>
 Detailed knowledge of industry standard EDA tools for Cadence.
 </li>
 <li>
 Experience with layout of high-performance memories of various types.
 </li>
 <li>
 Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)
 </li>
 <li>
 Experience with floor planning, block level routing and macro level assembly.
 </li>
 <li>
 Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.
 
 
 </li>
 </ul>
 We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
 
 
 JR1997057
 
 
</div>

Mask Designer

Qualcomm

<div><h2 class="jobSectionHeader">Company:</h2>
Qualcomm India Private Limited<h2 class="jobSectionHeader">
Job Area:</h2>
Engineering Group, Engineering Group &gt; Hardware Engineering
General Summary:<div>
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.</div>
Minimum Qualifications:<ul><li>Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
</li></ul>OR 
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
 
OR 
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.<ul><li>
Responsibilities<ul><li>
Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs</li><li>
RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.</li><li>
Work with functional verification team on test-plan development and debug.</li><li>
Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA.</li><li>
UPF writing, power aware equivalence checks and low power checks.</li><li>
DFT insertion and ATPG analysis for optimal SAF, TDF coverage.</li><li>
Provide support to SoC integration and chip level pre/post-silicon debug.</li></ul></li><li>
Skills &amp; Experience<ul><li>
MTech/BTech in EE/CS with hardware engineering experience of 3+ years.</li><li>
Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA.</li><li>
Experience with post-silicon bring-up and debug is a plus.</li><li>
Able to work with teams across the globe and possess good communication skills.</li></ul></li></ul>
Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
If you would like more information about this role, please contact Qualcomm Careers.</div>

MSIP Senior Digital Design Engineer

Apple

<div>Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish.
 
 
The people here at Apple don&rsquo;t just create products - they create the kind of wonder that&rsquo;s revolutionized entire industries. It&rsquo;s the diversity of those people and their ideas that inspires the innovation that runs through everything we do, from amazing technology to industry-leading environmental efforts. Join Apple, and help us leave the world better than we found it.
 
 
Apple products are as beautiful on the inside as they are on the outside. Inside every one of our products, are some of the world's most challenging consumer PCBA and Flex designs. Imagine yourself as a select member of the team that brings these assemblies from concept to high volume manufacturing. 
 
Description 
<ul><li>In this highly visible role, you will have the opportunity to make a significant impact on Apple Products, and leave a footprint for years to come. We have an opportunity for an accomplished PCBA DFM engineer to lead the development, and ramp for a next generation Apple product.</li></ul> 
<ul><li>Our PCBA DFM engineering team enables the mass creation of impossible products as a partner in the development of Apple's renowned designs.</li></ul> 
<ul><li>Key responsibilities will include:</li></ul> 
<ul><li>Attend development builds as required under direction of Operations Engineering Directly Responsible Individual (DRI).
</li></ul> 
<ul><li>May provide guidance and resources to contract manufacturing (CM) partner engineers.</li></ul> 
<ul><li>Acts as project leader on a variety of complex projects.</li></ul> 
<ul><li>Plans, develops and implements technically complex procedures for PCBA manufacturing process, rework, and testing.
</li></ul> 
<ul><li>Make recommendations for changes required in testing equipment (ICT and Functional test), manufacturing processes, and new testing requirements.</li></ul> 
<ul><li>Designs and develops technically complex new processes to improve quality and efficiency.</li></ul> 
<ul><li>Provides early manufacturing involvement to ensure new products are manufacturable. Activities include driving out costs in design/PCBA manufacturing tooling, influencing designs so that they are manufacturable, reducing complexity by using standard size packaging.</li></ul> 
<ul><li>Interface with Apple Printed Circuit Board Assembly (PCBA) Subcontractor and manage technical aspects of Volume Manufacturing builds including rework processes, with direction as necessary from Operations Engineering DRI.
</li></ul> 
<ul><li>Ensure Apple PCBA Subcontractors/JDM partner adherence to Process Parameters and Procedures as well as approved Manufacturing and Test processes. Ensure maintenance of specified quality levels at PCBA Manufacturing sites</li></ul> 
- Travel domestically and internationally to supplier sites - 30%&quot;,&quot;educationAndExperience&quot;:&quot;Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. 
 
Apple&rsquo;s most important resource, our soul, is our people. Apple benefits help further the well-being of our employees and their families in meaningful ways. No matter where you work at Apple, you can take advantage of our health and wellness resources and time-away programmes. We&rsquo;re proud to provide stock grants to employees at all levels of the company, and we also give employees the option to buy Apple stock at a discount - both offer everyone at Apple the chance to share in the company&rsquo;s success. You&rsquo;ll discover many more benefits of working at Apple, such as programmes that match your charitable contributions, reimburse you for continuing your education and give you special employee pricing on Apple products.
 
 
Apple benefits programmes vary by country and are subject to eligibility requirements. 
 
Preferred Qualifications 
Working knowledge of printed circuit board assembly (PCBA) reliability concepts, failure analysis techniques like EDX, SEM and FTIR. 
Experience with the development and evaluation of various SMT processes 
Project management experience and a deep understanding of problem solving tools including design of experiments, root cause analysis and statistical analytical tools 
Experience with any of the following: packaging technology, chip scale or wafer level chip scale packaging technology, molding process, System in package construction 
Effective communication skills with an ability to explain complex problems to a wide variety of technical and non-technical audiences 
Good team player with an ability to work with multiple x-functional teams 
 
Minimum Qualifications 
BS/MS in Mechanical, Electrical, Industrial, Chemical or Manufacturing Engineering with 5 to 6 years experience working in Printed circuit board assembly or with surface mount technology at a contract manufacturer or any related experience. 
5+ years of experience in printed circuit assembly manufacturing processes. 
Surface mount technology process knowledge including stencil printing, pick and placement process, reflow process, hotbar, robotic/laser soldering and ACF process. 
Experience developing process quality plans, supplier quality audits, and driving corrective actions and failure analysis efforts.&quot;,&quot;internalDetails&quot;:null,&quot;eeoContent&quot;:null</div>

Design for Manufacturing (DFM) Engineer - PCBA

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