soc design engineer

<div>Overview:
<div><b>
WHAT YOU DO AT AMD CHANGES EVERYTHING</b></div><div>
At AMD, our mission is to build great products that accelerate next-generation computing experiences&mdash;from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you&rsquo;ll discover the real differentiator is our culture. We push the limits of innovation to solve the world&rsquo;s most important challenges&mdash;striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. <b>Together, we advance your career.</b></div>
Responsibilities:
<div><b>
SMTS SILICON DESIGN ENGINEER</b><br>
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<b>THE ROLE:</b></div><div>
As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.<br>
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<b>THE PERSON:</b></div><div>
The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team.<br>
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<b>KEY RESPONSIBLITIES:</b></div><ul><li>
Design of IP and subsystems with integration of AMD and other 3rd party IPs</li><li>
Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs</li><li>
Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC</li><li>
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up</li></ul><div><b><br>
PREFERRED EXPERIENCE:</b></div><ul><li>
8-12 years full-time experience in IP hardware design</li><li>
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs</li><li>
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)</li><li>
Clock domain crossing (CDC) tools</li><li>
Detailed understanding of SoC design flows</li><li>
Understanding of IP/SS/SoC Power Management techniques &ndash; Power Gating, Clock Gating</li><li>
Experience with embedded processors and data fabric architectures (NoC)</li><li>
Outstanding interaction skills while communicating both written and verbally</li><li>
Ability to work with multi-level functional teams across various geographies</li><li>
Outstanding problem-solving and analytical skills</li></ul><div></div><div><b><br>
ACADEMIC CREDENTIALS:</b></div><ul><li>
Bachelors degree in Computer Engineering/Electrical Engineering plus 12 years full-time experience in IP hardware design, or Masters degree plus 8 years experience in same.</li></ul><p></p><p><br>
#LI-NS1</p>
Qualifications:
<div><i>
Benefits offered are described: </i>AMD benefits at a glance.</div><div></div><div><i><br>
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</i></div></div>

IP/ Subsystem Design Lead

NVIDIA

<div><p>We are now looking for a Senior ASIC Design Engineer - DFX</p><p></p><p>
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI &mdash; the next era of computing. NVIDIA is a &ldquo;learning machine&rdquo; that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life&rsquo;s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.</p><p></p><p><b>
What You&rsquo;ll Be Doing:</b></p><ul><li><p>
As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You&rsquo;ll help drive innovation across the full silicon lifecycle&mdash;from pre-silicon to post-silicon&mdash;while mentoring and collaborating with cross-functional teams.</p></li><li><p>
Own the architecture, design, and verification of DFT IPs for cutting-edge SoC designs.</p></li><li><p>
Develop, deploy, and enhance DFT methodologies for scalability and future product needs.</p></li><li><p>
Define and align feature sets by working closely with architects, platform, and software teams.</p></li><li><p>
Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.</p></li><li><p>
Create and execute test plans to support both functional and DFT full-chip verification.</p></li><li><p>
Support post-silicon bring-up and validation efforts including debug and issue resolution.</p></li><li><p>
Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.</p></li></ul><p></p><p><b>
What We need to see:</b></p><ul><li><p>
Master&rsquo;s degree (or equivalent experience) in Electrical Engineering or related field.</p></li><li><p>
5+ years of hands-on experience in SoC architecture, RTL design, and verification.</p></li><li><p>
Strong proficiency in micro-architecture and RTL development using Verilog.</p></li><li><p>
Experience with formal verification using JasperGold is a plus.</p></li><li><p>
Deep expertise in DFT design, methodology, and implementation.</p></li><li><p>
Familiarity with related domains such as clocking, STA, place &amp; route, and power optimization.</p></li><li><p>
Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.</p></li><li><p>
Proficiency in scripting languages such as Python, Perl, or Tcl.</p></li><li><p>
Excellent communication skills and a collaborative mindset&mdash;with a curiosity and passion for solving complex technical challenges.</p></li></ul><p></p><p>
This is your chance to join a high-impact team driving the foundation of next-generation semiconductor innovation. If you&rsquo;re passionate about DFT and SoC architecture, and want to work in a fast-paced, collaborative environment where your ideas make a difference&mdash;we&rsquo;d love to hear from you.</p><p></p>
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.<p></p><div><div><div><div><div><div><div><p>
You will also be eligible for equity and benefits.</p></div></div></div></div></div></div></div><p></p>
Applications for this job will be accepted at least until October 28, 2025.<p></p>
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.</div><p></p>

Senior ASIC Design Engineer - DFX

Amazon Web Services

<div><h2 class="jobSectionHeader"><b>DESCRIPTION</b></h2><div>
Utility Computing (UC)<br>
AWS Utility Computing (UC) provides product innovations &mdash; from foundational services such as Amazon&rsquo;s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS&rsquo;s services and features apart in the industry. As a member of the UC organization, you&rsquo;ll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for customers who require specialized security solutions for their cloud services.<br>
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Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago&mdash;even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.<br>
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About AWS<br>
Amazon Web Services (AWS) is the world&rsquo;s most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating &mdash; that&rsquo;s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.<br>
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Diverse Experiences<br>
AWS values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn&rsquo;t followed a traditional path, or includes alternative experiences, don&rsquo;t let it stop you from applying.
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Work/Life Balance<br>
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there&rsquo;s nothing we can&rsquo;t achieve in the cloud.
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Inclusive Team Culture<br>
Here at AWS, it&rsquo;s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon (gender diversity) conferences, inspire us to never stop embracing our uniqueness.<br>
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Mentorship &amp; Career Growth<br>
We&rsquo;re continuously raising our performance bar as we strive to become Earth&rsquo;s Best Employer. That&rsquo;s why you&rsquo;ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
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Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.<br>
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Key job responsibilities<br>
<ul><li>integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing</li><li>As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.</li><li>Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.</li><li>Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.</li><li>Perform lint and clock domain crossing quality checks on the design.</li></ul>
- Work with with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.<br>
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You will thrive in this role if you:<br>
<ul><li>Are familiar with scripting in Python</li><li>Are proficient with assertions</li><li>Have good debug skills to analyze RTL test failures</li><li>Have a &quot;Learn and Be Curious&quot; mindset</li></ul><br>
About the team<br>
Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you&rsquo;ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we&rsquo;re handling massive scale and rapid integration of emergent technologies. We&rsquo;re looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.<br>
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Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we&rsquo;re building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews. We care about your career growth and strive to assign projects that help our team members develop your engineering expertise so you feel empowered to take on more complex tasks in the future.</div><h2 class="jobSectionHeader"><b>
BASIC QUALIFICATIONS</b></h2><ul><li>BS degree in electrical engineering or equivalent</li><li>3+ years in RTL design for SOC</li><li>3+ years of VLSI engineering</li><li>3+ years with code quality tools including: Spyglass, LINT, or CDC</li></ul><h2 class="jobSectionHeader"><b>
PREFERRED QUALIFICATIONS</b></h2><ul><li>Experience scripting for automation (e.g., Python, Perl, Ruby)</li><li>Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints</li><li>Familiarity with data path design, interconnects, AXI protocol</li><li>Good analytical, problem solving, and communication skills</li></ul><br>
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.<br>
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Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.<br>
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Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner.<br>
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Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $129,800/year in our lowest geographic market up to $212,800/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits. This position will remain posted until filled. Applicants should apply via our internal or external career site.</div>

ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Concentrix

<div><div><div><p><b>Global Security
</b></p></div><div><div><div><b>Location</b></div>
<div>Gurugram, India</div></div></div><div></div><div><div><br>
</div><p>Job Title:</p>
SOC Engineering &ndash; Product &amp; Automation<p>
Job Description</p>
We are looking for a SOC Product &amp; Automation Engineer to join our CDOC Engineering team. The role will focus on SIEM engineering and SOAR automation, with hands-on expertise in Palo Alto XSIAM and XSOAR. You&rsquo;ll design and optimize automation playbooks, build SIEM detections, and work closely with MSS SOC and clients to deliver scalable, efficient security operations.<h3 class="jobSectionHeader"><b>
Job Title:</b><b> SOC Product &amp; Automation Engineer</b></h3><div><b>
Location:</b> On-site &ndash; Gurgaon, Cyber City<br>
<b>Experience Required:</b> 4&ndash;5 years<br>
<b>Department:</b> CDOC Engineering</div><h3 class="jobSectionHeader"><b>
Role Overview</b></h3><div>
We are seeking a skilled <b>SOC Product &amp; Automation Engineer</b> with 4&ndash;5 years of experience in <b>SIEM engineering</b> and <b>SOAR automation</b>. The role requires hands-on expertise in <b>Palo Alto XSIAM and XSOAR</b>, focusing on building, optimizing, and maintaining automation frameworks to enhance SOC operations. This is an <b>on-site position in Gurgaon (Cyber City)</b>, requiring close collaboration with CDOC Engineering and MSS SOC teams.</div><h3 class="jobSectionHeader"><b>
Key Responsibilities</b></h3><ul><li><div>
Design, build, and maintain <b>SIEM use cases</b> and detections within <b>Palo Alto XSIAM</b>.</div></li><li><div>
Develop, test, and manage <b>SOAR playbooks</b> and integrations in <b>XSOAR</b> to automate SOC workflows.</div></li><li><div>
Partner with MSS SOC and engineering teams to deliver automation for <b>incident response and threat management</b>.</div></li><li><div>
Support <b>POCs and client engagements</b>, ensuring solutions meet security and business requirements.</div></li><li><div>
Optimize existing automation to improve SOC efficiency and reduce manual workload.</div></li><li><div>
Provide <b>Level 3 engineering support</b> for automation-related escalations.</div></li><li><div>
Document automation processes, playbooks, and engineering standards for reuse and scalability.</div></li></ul><h3 class="jobSectionHeader"><b>
Required Skills &amp; Experience</b></h3><ul><li><div>
4&ndash;5 years of experience in <b>SIEM engineering</b> and <b>SOAR automation</b>.</div></li><li><div>
Strong hands-on expertise with <b>Palo Alto XSIAM and XSOAR</b> (mandatory).</div></li><li><div>
Proficiency in developing automation playbooks, integrations, and APIs.</div></li><li><div>
Knowledge of scripting languages such as <b>Python</b> or <b>JavaScript</b>.</div></li><li><div>
Strong understanding of <b>SOC operations, incident response, and threat detection workflows</b>.</div></li><li><div>
Familiarity with security frameworks (e.g., <b>MITRE ATT&amp;CK, NIST</b>).</div></li><li><div>
Excellent troubleshooting and problem-solving skills.</div></li></ul><h3 class="jobSectionHeader"><b>
Nice-to-Have</b></h3><ul><li><div>
Exposure to other SIEM/SOAR platforms (Splunk, QRadar, Sentinel, etc.).</div></li><li><div>
Experience in <b>Managed Security Services (MSS)</b> or client-facing SOC environments.</div></li><li><div>
Relevant certifications: <b>PCSCE, PCNSE, or equivalent</b>.</div></li></ul><h3 class="jobSectionHeader"><b>
What We Offer</b></h3><ul><li><div>
Opportunity to work on cutting-edge <b>XSIAM/XSOAR implementations</b>.</div></li><li><div>
Exposure to <b>global MSS clients</b> and enterprise security environments.</div></li><li><div>
Career growth in <b>SOC engineering, automation, and product development</b>.</div></li></ul><p>
Location:</p>
IND Gurgaon - Bld 14 IT SEZ Unit 1, 5th, 6th and 17th Flr<p>
Language Requirements:</p><p>
Time Type:</p>
Full time<p><b>
If you are a California resident, by submitting your information, you acknowledge that you have read and have access to the </b><b>Job Applicant Privacy Notice for California Residents</b></p></div></div></div><div></div>

SOC Engineering – Product & Automation

My Delivery Services Co.

<p>The Full Stack ENGINEER will be responsible for designing, developing, and maintaining scalable web applications using the MERN stack (MongoDB, Express.js, React.js, Node.js). The role requires expertise in both front-end and back-end development, with an emphasis on clean code, performance optimization, and adherence to compliance standards.<br/><b>Key Responsibilities</b></p><ul><li>Design and implement end-to-end web applications using MERN stack.</li><li>Develop responsive UI components using React.js and integrate with RESTful/GraphQL APIs. &bull; Build and optimize backend services using Node.js and Express.js.</li><li>Implement and manage databases with MongoDB including schema design and performance tuning.</li><li>Ensure code quality, reusability, and maintainability through best practices and code reviews.</li><li>Collaborate with QA engineers to ensure software meets quality and compliance standards (SOC 2 / ISO).</li><li>Debug, troubleshoot, and resolve technical issues in a timely manner</li><li>Stay up to date with emerging technologies and apply them where relevant.</li><li>Responsibilities are not limited to the above and may evolve as per business needs.</li></ul><p><b>Qualifications &amp; Skills</b></p><ul><li>Bachelor&rsquo;s degree in Computer Science, Software Engineering, or equivalent experience. 3+ years of professional experience as a MERN developer. &bull; Strong proficiency in JavaScript/TypeScript, React.js, Node.js, Express.js, and MongoDB. Experience with RESTful APIs and GraphQL integrations. Knowledge of CI/CD, Git workflows, and cloud deployment (AWS, Vercel, or similar). &bull; Understanding of application security principles and compliance requirements (SOC 2 / ISO). Excellent problem-solving skills and attention to detail. Qualifications and skills are not limited to the above and equivalent experience may be considered.</li></ul><p><b>Performance Indicators</b></p><ul><li>Timely delivery of high-quality, fully functional web applications.</li><li>Code quality, maintainability, and adherence to industry standards.</li><li>Minimal defects and efficient resolution of issues.</li></ul><p>| &bull; Positive collaboration and knowledge sharing within the team.</p><ul><li>Compliance with SOC 2 / ISO standards in coding and documentation</li></ul><p>Job Type: Full-time</p><p>Work Location: In person</p>

MERN Stack Engineer

Bazzle Balloons

<p><b>2. SOC Engineer / Cyber Security Engineer</b></p><p><b>Certifications Required:</b> CEH, CompTIA Security+, SOC Handling, SIEM Implementation</p><p>&middot; Vendor-specific certifications: <b>ELK, QRadar, Wazuh</b> (advantage)</p><p>&middot; <b>Fortinet NSE, Cisco CyberOps, </b>(plus)</p><p>At least four years Bachelors in IT / Computer Science / Telecom/ Engineering</p><p>Experience: <b>3-4 years</b> of relevant professional experience in <b>SOC operations, cyber security, or incident response.</b></p><p><b>Responsibilities:</b></p><p>&middot; Monitor <b>real-time threats</b> and handle <b>security incidents</b> across Client IT systems using advanced SOC tools.</p><p>&middot; Deploy, configure, and manage <b>SIEM solutions</b> (Wazuh, Splunk, ELK, QRadar, etc.) for <b>log collection, analysis, intrusion detection, and anomaly reporting</b>.</p><p>&middot; Perform <b>malware analysis, digital forensics, and evidence preservation</b> to support <b>cybercrime investigations</b>.</p><p>&middot; Implement and integrate <b>threat intelligence feeds</b> tailored for <b>law enforcement use cases</b>.</p><p>&middot; Utilize frameworks such as <b>MITRE ATT&amp;CK and NIST</b> for <b>incident detection, classification, and response</b>.</p><p>&middot; Conduct <b>forensic investigations</b> with tools such as <b>Volatility, Autopsy, Ghidra, and IDA Pro</b>.</p><p>&middot; Carry out <b>vulnerability assessments, penetration testing, and remediation planning</b>.</p><p>&middot; Monitor and tune <b>firewalls, IDS/IPS, and VPN security</b> systems.</p><p>&middot; Familiarity with security tools and devices.</p><p>&middot; Support <b>law enforcement digital platforms</b> (CCTV, bodycams, and surveillance systems) by securing <b>data pipelines</b> and ensuring <b>data integrity</b>.</p><p>&middot; Conduct <b>awareness sessions</b> for Client officers on phishing, ransomware, and <b>cyber hygiene best practices</b>.</p><p>&middot; Collaborate with Client units for <b>proactive threat hunting and incident response</b>.</p><p>&middot; Manage the full <b>incident response lifecycle</b>: detection, triage, containment, eradication, recovery, and reporting.</p><p>&middot; Prepare <b>incident reports, forensic documentation, and compliance reviews</b> for audits and investigations.</p><p>&middot; Provide <b>IT assistance during emergency response operations</b>.</p><p>&middot; Perform any other tasks assigned by <b>Client</b>.</p><p>Job Type: Full-time</p><p>Application Question(s):</p><ul><li>Your degree Bachelors in IT / Computer Science / Telecom/ Engineering  completed? </li><li>Do you have 4 years of relevant professional experience in SOC operations, cyber security, or incident response?</li><li>Do you have a certificate of Fortinet NSE, Cisco CyberOps?</li></ul><p>License/Certification:</p><ul><li>CEH, certificate of CompTIA Security (Required)</li></ul><p>Work Location: In person</p>

SOC Engineer / Cyber Security Engineer

ZIEL Global Private Limited

<p><b>About the Role</b><br/>We&rsquo;re seeking a <b>DevOps Engineer</b> to design and maintain scalable, secure infrastructure across global operations. The ideal candidate will automate deployments, optimize cloud usage, enforce compliance, and ensure 24/7 reliability.</p><p><b>Key Responsibilities</b></p><ul><li>Design and manage cloud infrastructure (preferably Azure)</li><li>Implement Infrastructure as Code (Terraform, ARM, or similar)</li><li>Build and maintain CI/CD pipelines with Azure DevOps or GitHub Actions</li><li>Configure monitoring, logging, and alerting for mission-critical systems</li><li>Enforce security standards, compliance policies, and access control</li><li>Document infrastructure, deployment, and recovery processes</li></ul><p><b>Qualifications</b></p><ul><li>Bachelor&rsquo;s in Computer Science, IT, or related field</li><li>5+ years of DevOps or cloud infrastructure experience</li><li>Deep understanding of Azure compute, networking, and security services</li><li>Proficiency in containerization (Docker, Kubernetes)</li><li>Experience with automation scripts (Bash, PowerShell, Python)</li><li>Strong focus on documentation, scalability, and security</li></ul><p><b>Preferred</b></p><ul><li>Azure certifications (DevOps Engineer, Security Engineer)</li><li>Knowledge of compliance frameworks (ISO 27001, SOC 2, GDPR)</li></ul><p>Job Type: Full-time</p><p>Application Question(s):</p><ul><li>Are you available to join immediately?</li><li>How would you rate your English communication skills, spoken and written?</li><li>What are your salary expectations?</li></ul><p>Work Location: In person</p>

DevOps Engineer

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