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Senior Engineer - CAD (Physical Verification )
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Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at .
Meet the Team
The Central CAD Physical Verification (PV) team develops and maintains industry-leading verification methodologies that ensure Silicon Labs’ designs meet foundry and internal quality requirements. The team owns development of PV rule decks—including DRC, antenna, dummy fill, LVS, extraction, and custom checks—and partners closely with design, layout, CAD, ESD, and foundry teams. We also drive automation and flow improvements to enhance verification quality, scalability, and performance.
Responsibilities
- Develop and maintain physical verification rule decks (e.g., DRC, dummy fill, antenna, and other custom checks).
- Lead impact analysis and review sessions with cross-functional stakeholders for deck changes and updates.
- Collaborate with CAD, ESD, design, layout, and foundry teams to gather requirements and translate them into robust PV rules.
- Support design/layout teams in debugging PV issues throughout the design cycle.
- Perform code reviews and create QA testcases to ensure rule-deck quality and consistency.
- Develop, enhance, and maintain PV flows and methodologies for improved performance and verification coverage.
- Evaluate new tools/features and perform benchmarking to guide methodology improvements.
- Work with EDA vendors to identify, report, and track tool-related issues.
Skills You’ll Need
- 3+ years of relevant experience in physical verification or CAD development.
- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- Strong experience developing DRC decks using Calibre SVRF (or similar rule-deck languages).
- Hands-on experience with Calibre RVE/DRV, Virtuoso layout editor, or equivalent PV tools.
- Experience with LVS and PERC rule-deck development is a plus.
- Experience collaborating with design/layout teams to debug PV issues.
- Proficiency in scripting languages such as Python, Perl, or Shell.
- Strong analytical, documentation, and communication skills; ability to work independently and drive decisions.
Benefits & Perks
At Silicon Labs, you’ll be part of a highly skilled team where every engineer makes a meaningful impact. We promote work-life balance and a welcoming, fun environment.
At Silicon Labs, you’ll be part of a highly skilled team where every engineer makes a meaningful impact. We promote work-life balance and a welcoming, fun environment.
- Equity Rewards (RSUs)
- Employee Stock Purchase Plan (ESPP)
- Insurance plans with outpatient cover
- National Pension Scheme (NPS)
- Flexible work policy
- Childcare support
Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.
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