Senior Engineer- RTL

Lead RTL design activities for complex digital blocks and guide the team from architecture to tape-out.

Key Responsibilities:
Own and develop RTL for complex digital designs
Define micro-architecture and review design specifications
Lead code reviews and ensure high-quality, synthesizable RTL
Work closely with verification, architecture, and backend teams
Drive timing, power, and area–aware RTL design
Support integration, debug, and silicon bring-up activities

Required Skills & Experience:
6–9 years of experience in RTL design
Strong proficiency in Verilog / SystemVerilog
Experience with SoC / IP-level design
Good understanding of synthesis and timing concepts
Experience mentoring junior engineers
Low-power design knowledge (UPF / CPF)
Exposure to DFT and formal verification

Required Skills & Experience:
3–6 years of experience in RTL design
Strong proficiency in Verilog / SystemVerilog
Experience with SoC / IP-level design
Good understanding of synthesis and timing concepts
Experience mentoring junior engineers
Low-power design knowledge (UPF / CPF)
Exposure to DFT and formal verification