Senior Silicon CAD Methodology Engineer, Google Cloud

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Minimum qualifications:

Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
5 years of experience in ASIC/SoC design or CAD/EDA methodology, or EDA research and development/product engineering.
Experience in programming languages such as Python or C++.
Experience in developing and supporting end-to-end chip design flows.

Preferred qualifications:

8 years of experience in ASIC/SoC design or CAD/EDA methodology, or EDA research and development/product engineering.
Experience in developing methodologies or flows specifically for 3DIC technology.
Experience with cadence integrity 3DIC platform or synopsys 3DIC compilers.

About the job

Be part of a various team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

Lead architecture and implementation of advanced PDCAD flows, enabling methodologies through automation tools.
Optimize design flows for 3 Dimensional Integrated Circuit (3DIC) and advanced packaging to ensure manufacturability.
Drive evaluation and integration of Electronic Design Automation (EDA) tools like Integrity 3DIC or synopsys 3DIC compiler from flow development point of view.
Partner with global teams to standardize best practices in chip design flow techniques.
Lead complex technical projects from concept to closure and mentor junior engineers.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

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