VLSI Design Verification Engineer

Job Role: VLSI Design Verification Engineer

Required Skill: SystemVerilog, VLSI DV

Experience: 4-7 years
Location: Hyderabad/ Bangalore
Must Have Skill:

• 3+ years Design Verification experience in SystemVerilog / C++
• Experience in test planning and debugging complex designs
• Full silicon design lifecycle experience
• Strong background in developing UVM Testbenches from scratch
• Deep understanding of Computer Architecture

Good To Have: Experience with caches and memory subsystems

Roles & Responsibility : Job requires experience in VLSI DV skills.