Location:
Lahore, on-site
Job Type:
Full-time
Industry:
Semiconductor, Design Verification
This is an exciting opportunity to work with an experienced and highly motivated team of verification engineers.
Key Responsibilities:
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Developing and executing testplans for complex IPs
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Collaborate with the design and verification teams to ensure comprehensive coverage.
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Utilize advanced verification methodologies to identify and resolve design issues.
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Contribute to the continuous improvement of verification processes and methodologies.
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Participate in code reviews and provide feedback on verification-related aspects.
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Maintain thorough documentation of verification activities and results.
Minimum Qualification:
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Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field
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1+ years of working experience
Mandatory Skills:
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RISC V assembly language and C language expertise for low level programming
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Hands of experience with RISC V Priv/Unpriv architecture is must
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Good understanding computer architecture concepts
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Experience with hypervisors and virtualization is add plus
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Experience with testplan development and implementation
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Knowledge of Verilog/System Verilog
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Familiarity with industry-standard verification tools
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Ability to work in a fast-paced and collaborative environment
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Strong communication and collaboration abilities
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Excellent problem-solving skills and attention to detail.
Desired Skills:
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Expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
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Proficiency in testbench development and verification methodologies.
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Strong understanding of the verification life cycle.
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Good understanding of advance computer architecture concepts such as Branch predication, out-of-order processors, cache coherency, memory consistency models
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Contributions to RISC-V open-source projects such as arch-test development