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design verification engineer

Apple

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple&rsquo;s premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love to have you join us 
 
Description 
 
As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all teams (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design &amp; micro-architecture teams. A key component to the job is understanding the functional &amp; performance goals of the design and you use this knowledge to test effectively. You develop test plans, tests &amp; coverage plans as well as define our next generation verification methodology &amp; testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results. 
 
Preferred Qualifications 
 
Knowledge of computer architecture and digital design fundamentals 
 
Knowledge of Verilog or SystemVerilog, digital simulation and debug 
 
Experience with Python, Perl, or similar scripting language 
 
Ability to work independently to deliver the project goals 
 
Experience with C/C++, assembly is a plus. 
 
Excellent interpersonal skills and the dream to take on diverse challenges 
 
Minimum Qualifications 
 
Minimum of BS + 0 years relevant industry experience. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $190,900, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Design Verification Engineer

At Apple we work every single day to craft products that enrich people&rsquo;s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple&rsquo;s customers every single day. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be required to do physical designs of outstanding PHY design. 
 
Description 
 
As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration. 
 
Preferred Qualifications 
 
Deep design experience in high PHY and/or SOC designs. 
 
Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place &amp; Route. 
 
Experience in developing and implementing Power-grid and Clock specifications. 
 
Strong understanding of all aspects of Physical construction, Integration and Physical Verification. 
 
Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design &amp; Synthesis tools. 
 
Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools. 
 
Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level. 
 
Minimum Qualifications 
 
Bachelors of Science in Electrical Engineering. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $220,900, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Physical Design Engineer

At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class Apple mixed-signal silicon design team! 
 
This role will build upon your solid foundation in digital logic circuits while introducing mixed-signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits, ensuring formal equivalence between custom designs and their abstract representations. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry. 
 
As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits with signal processing capabilities. 
 
Description 
 
In this role, you will be responsible for specifying and/or micro-architecting digital and signal processing blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others, including implementation of DSP algorithms. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, and validating signal processing performance.&quot;,&quot;responsibilities&quot;:&quot;RTL Design &amp; Implementation: Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal processing pipelines 
 
DSP Algorithm Translation: Collaborate with algorithm engineers to translate DSP concepts (filtering, transforms, modulation, signal analysis) into efficient, high-performance RTL implementations 
 
Design Verification: Write comprehensive assertions, unit-level testbenches, and participate in functional verification using industry-standard methodologies 
 
Integration &amp; Bring-up: Partner with cross-functional teams to integrate complex IPs, validate performance in silicon, and support lab characterization 
 
Collaborative Problem-Solving: Work effectively with analog designers, algorithm engineers, verification specialists, and system architects across disciplinary boundaries 
 
Preferred Qualifications 
 
Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers) 
 
Synthesis, static timing analysis, and design-for-test (DFT) 
 
SystemVerilog assertions, checkers, and advanced verification techniques 
 
Scripting languages (Perl, Python) 
 
Formal verification and low-power design methodologies 
 
Hardware-software co-design and system-level optimization 
 
Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing) 
 
Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design 
 
Minimum Qualifications 
 
Bachelors of Science in Electrical Engineering. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $220,900, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

RTL Design Engineer

Amazon Web Services

<div><h2 class="jobSectionHeader">DESCRIPTION</h2><div>
Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power today's AI workloads across datacenters worldwide. As an ASIC Design Methodologies and Infrastructure Engineer, you'll play a foundational role in the project by automating design flows and building large-scale solutions that accelerate silicon development and we're just getting started here at Amazon! 
 
We're looking for a strong engineer who is passionate about creating design flows and automation flows that enhance both the productivity and quality of our design team. The ideal candidate brings proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving and automating flows. In this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality. 
Key job responsibilities 
 
Core Responsibilities: 
 
<ul><li>Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards.</li><li>Enhance and build design flows to boost the overall productivity of design teams.</li><li>Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.</li></ul> 
About the team 
Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago&mdash;even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help
 
 
Diverse Experiences 
Annapurna values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasn&rsquo;t followed a traditional path, or includes alternative experiences, don&rsquo;t let it stop you from applying. 
 
Work/Life Balance 
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why we strive for flexibility as part of our working culture. When we feel supported in the workplace and at home, there&rsquo;s nothing we can&rsquo;t achieve in the cloud. 
 
Inclusive Team Culture 
Here at Annapurna, it&rsquo;s in our nature to learn and be curious. Our employee-led affinity groups foster a culture of inclusion that empower us to be proud of our differences. Ongoing events and learning experiences, including our Conversations on Race and Ethnicity (CORE) and AmazeCon conferences, inspire us to never stop embracing our uniqueness. 
 
Mentorship &amp; Career Growth 
We&rsquo;re continuously raising our performance bar as we strive to become Earth&rsquo;s Best Employer. That&rsquo;s why you&rsquo;ll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
</div><h2 class="jobSectionHeader">BASIC QUALIFICATIONS</h2><ul><li>7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience</li><li>7+ years of digital design in communication systems experience</li><li>7+ years of full-custom analog or RF layout experience</li><li>7+ years of wireless communications systems and implementation experience</li><li>8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience</li><li>7+ years of verification in communication systems experience</li><li>5+ years of UVM, C, System C, and scripting experience</li></ul><h2 class="jobSectionHeader">
PREFERRED QUALIFICATIONS</h2><ul><li>Master's degree or Ph.D. degree in Electrical Engineering or related field</li><li>Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs</li><li>Experience with modern ASIC/FPGA design and verification tools</li><li>Experience with SOC bring-up and post-silicon validation</li></ul> 
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. 
 
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. 
 
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner. 
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life &amp; AD&amp;D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits. 
USA, CA, Cupertino - 183,000.00 - 247,600.00 USD annually 
USA, TX, Austin - 159,200.00 - 215,300.00 USD annually</div>

Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

<div><h2 class="jobSectionHeader">DESCRIPTION</h2><div>
AWS's Trainium and Inferentia chips power the world's largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. We're looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production. 
 
What you'll do: 
 
<ul><li>Build and own models of SoC subsystems &mdash; translating architecture specs and RTL behavior into accurate, testable C++ models</li><li>Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows</li><li>Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing</li><li>Contribute to performance modeling efforts &mdash; building cycle-approximate models that help architects evaluate design trade-offs before RTL exists</li><li>Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams</li><li>Collaborate with chip architects to understand upcoming designs and plan modeling work ahead of RTL availability</li></ul> 
Why this role is interesting: 
 
<ul><li>Your models are used to verify silicon before it's built &mdash; bugs you catch save months of schedule and millions of dollars</li><li>You'll work at the intersection of software engineering and chip design, with deep visibility into how custom ML accelerators are architected</li><li>As the team scales, there's a clear path into architectural modeling &mdash; using your models to influence chip design decisions, not just validate them</li><li>Small team, high ownership, direct impact on AWS's most strategic silicon programs</li></ul> 
You will thrive in this role if you: 
 
<ul><li>Have built functional or performance models of SoCs, ASICs, GPUs, CPUs, or IP blocks</li><li>Are comfortable working with architectural / design specifications or reference implementations and translating them into C++ or SystemC models</li><li>Understand verification concepts and have worked with DV teams or in pre-silicon validation environments</li><li>Care about model fidelity and have experience correlating models against RTL or silicon</li><li>Are interested in expanding into architectural performance modeling as the team grows</li><li>Enjoy working on a small, high-impact team where you own significant pieces of the stack</li></ul> 
No ML background needed. You'll learn the ML accelerator domain on the job. 
 
This role can be based in Cupertino, CA or Austin, TX.</div><h2 class="jobSectionHeader">
BASIC QUALIFICATIONS</h2><ul><li>Experience programming languages such as C/C++, Python, Java or Perl</li><li>2+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)</li><li>Familiarity with SoC, CPU, GPU, and/or ASIC architecture and micro-architecture</li></ul><h2 class="jobSectionHeader">
PREFERRED QUALIFICATIONS</h2><ul><li>2+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience</li><li>Experience working with DV teams or integrating models into verification flows</li><li>Experience with SystemC or TLM-based modeling</li><li>Experience correlating functional models against RTL simulation or emulation</li><li>Experience developing or calibrating performance models</li><li>Familiarity with Modern C++ (20 and beyond)</li><li>Experience with PyTest, GoogleTest, or similar test frameworks</li><li>Experience with multi-threaded simulation</li></ul> 
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. 
 
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company&rsquo;s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records. 
 
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you&rsquo;re applying in isn&rsquo;t listed, please contact your Recruiting Partner. 
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life &amp; AD&amp;D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits. 
USA, CA, Cupertino - 165,200.00 - 223,600.00 USD annually 
USA, TX, Austin - 143,700.00 - 194,400.00 USD annually</div>

Pre-Silicon SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS

We are looking for a SerDes System Validation Engineer to lead system validation of mixed-signal SerDes IP. In this highly visible role, you will actively work within Analog-Mixed/Signal design team and participate in validation and debug of embedded circuits; collaborating with many teams to enable the world&rsquo;s premiere products. You will closely work with a hard-working group of Analog-Mixed/Signal designers working diligently to deliver hard IPs to Apple&rsquo;s products while exceeding the highest expectations of quality, innovation and efficiency. 
 
At Apple, we work every day to craft products that enrich people&rsquo;s lives. In doing so, we face exciting challenges driven by the increasing complexity of SoC and PHY design. If you have strong technical fundamentals and a proven record of tackling complex problems-fueled by curiosity, a passion for learning, and a desire to enhance the impact of your work-we&rsquo;d love to hear from you. 
 
If you thrive on understanding the bigger picture while diving deep into the details to innovate and find elegant solutions. You enjoy collaborating with diverse teams to achieve extraordinary results, maintaining a strong team spirit even when facing tough challenges. Most importantly, you care about society and demonstrate leadership through your commitment to meaningful causes. 
 
We have an opportunity for a forward-thinking and especially hardworking system validation engineer with strong background in high-speed serial links. As a member of our dynamic team, you will have the rare and rewarding opportunity to work on upcoming products that will surprise and delight millions of Apple&rsquo;s customers every day. 
 
And all of this while enjoying a great culture where you own your career. 
 
Description 
 
Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in system. 
 
Work with design teams to understand the architecture and define DFT needs to help enhance testability and first-time silicon success. 
 
Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic. 
 
Preferred Qualifications 
 
Able to think outside of the box and come up with creative solutions for system validation. 
 
Knowledge of system level considerations e.g. ESD requirements. 
 
Very knowledgeable about and experienced with common high-speed SerDes protocols (e.g., PCIe, USB, UCIe, OIF, etc.). 
 
Experience with system bring-up of high-speed serial links, lab testing, and defining equipment needs. 
 
Very knowledgeable in scripting (e.g. python, C, Matlab) for automation of validation efforts. 
 
Experience with system level S/W setup. 
 
Experience in mixed-signal circuit pre-silicon verification and ability to closely work with circuit design team. 
 
Knowledge of DFT to aid in the system validation. 
 
Experience in leading mixed-signal SerDes system validation. 
 
Experience with silicon bring-up, debug and production ramp. 
 
Knowledge of SerDes design and architecture including CDR and equalization. 
 
Knowledge of with Tx/Rx equalization techniques and adaptation. 
 
Knowledge of link jitter budget for high-speed serial links and key block level requirements. 
 
Knowledge of ADC based links and equalization techniques. 
 
Familiarity with PCB design and specifications. 
 
Strong communication, teamwork and problem-solving skills. 
 
Proven track record of delivering under difficult debug and validation scenarios. 
 
Minimum Qualifications 
 
Minimum requirement of a bachelors degree. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $220,900, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

SerDes System Validation Engineer

<div>Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you&rsquo;ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You&rsquo;ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you&rsquo;ll be responsible for crafting and building the technology that fuels Apple&rsquo;s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role, you will be at the center of a semiconductor design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. 
 
Description 
 
As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. 
 
<ul><li>Developing and implementing DFT architecture</li></ul> 
<ul><li>Implementing DFT infrastructure</li></ul> 
<ul><li>Working with the DV team to verify DFT implementations and implement ECOs</li></ul> 
<ul><li>Generating structural test vectors and analyzing and improving coverage</li></ul> 
<ul><li>Working with designers on STA, physical, power and logical issues</li></ul> 
<ul><li>Working with test engineers to bring up test vectors on silicon</li></ul> 
<ul><li>Running schedules and supporting multi-functional engineering efforts</li></ul> 

Preferred Qualifications 
 
Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time. 
 
Experience developing DFT specifications and driving DFT architecture and methods for designs. 
 
Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools. 
 
Knowledge of industry standards for DFT and design tools. 
 
Proven Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon. 
 
Experience in debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issues. 
 
Experience with STA constraints development and analysis for DFT modes and SDF simulations. 
 
Ability to conduct experiments during silicon debug, gathering and analyzing data; and use scripting to support efficient handling of ATE data. 
 
Minimum Qualifications 
 
Minimum of BS + 0 years relevant industry experience. 
 
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . 
 
Pay &amp; Benefits 
 
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $121,300 and $183,200, and your base pay will depend on your skills, qualifications, experience, and location. 
 
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. 
 
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.</div>

SoC DFT Engineer

Explore 88+ Design verification engineer in Cupertino this April. Find roles across top companies and apply now to boost your career.